Patents by Inventor Shunpei Yamazaki

Shunpei Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387394
    Abstract: A positive electrode active material that is stable in a high potential state or a high temperature state and a highly safe secondary battery are provided. The positive electrode includes a first material and a second material and includes a region where at least part of a surface of the first material is covered with the second material. The first material includes a lithium cobalt oxide containing magnesium, fluorine, aluminum, and nickel. The second material includes a composite oxide (containing one or more selected from Fe, Ni, Co, and Mn) having an olivine crystal structure.
    Type: Application
    Filed: October 13, 2021
    Publication date: November 30, 2023
    Inventors: Shunpei YAMAZAKI, Tetsuya KAKEHATA, Shuhei YOSHITOMI, Atsushi KAWATSUKI
  • Publication number: 20230387130
    Abstract: A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.
    Type: Application
    Filed: August 17, 2023
    Publication date: November 30, 2023
    Inventors: Shunpei YAMAZAKI, Kensuke YOSHIZUMI
  • Publication number: 20230387276
    Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.
    Type: Application
    Filed: June 27, 2023
    Publication date: November 30, 2023
    Inventors: Toshinari SASAKI, Junichiro SAKATA, Hiroki OHARA, Shunpei YAMAZAKI
  • Publication number: 20230389332
    Abstract: A ferroelectric device having favorable ferroelectricity is provided. The ferroelectric device includes a first conductor over a first insulator, a ferroelectric layer over the first conductor, a second conductor over the ferroelectric layer, a second insulator over the second conductor, and a third insulator surrounding the first conductor, the ferroelectric layer, the second conductor, and the second insulator. The second insulator has a function of capturing or fixing hydrogen, and the third insulator has a function of inhibiting hydrogen diffusion.
    Type: Application
    Filed: October 11, 2021
    Publication date: November 30, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Yasuhiro JINBO, Toshikazu OHNO, Yuichi SATO, Sachie ETO, Shinobu KAWAGUCHI
  • Publication number: 20230387217
    Abstract: A novel material is provided. A composite oxide semiconductor includes a first region and a second region. The first region contains indium. The second region contains an element M (the element M is one or more of Ga, Al, Hf, Y, and Sn). The first region and the second region are arranged in a mosaic pattern. The composite oxide semiconductor further includes a third region. The element M is gallium. The first region contains indium oxide or indium zinc oxide. The second region contains gallium oxide or gallium zinc oxide. The third region contains zinc oxide.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 30, 2023
    Inventors: Shunpei YAMAZAKI, Yasuharu HOSAKA, Yukinori SHIMA, Junichi KOEZUKA, Kenichi OKAZAKI
  • Patent number: 11830880
    Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 28, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11830391
    Abstract: A novel display panel that is highly convenient, useful, or reliable is provided. The display panel includes a display region, a first support, and a second support, the display region includes a first region, a second region, and a third region, the first region and the second region each have a belt-like shape extending in one direction, and the third region is sandwiched between the first region and the second region. The first support overlaps with the first region and is less likely to be warped than the third region, and the second support overlaps with the second region and is less likely to be warped than the third region. The second support can pivot on an axis extending in the one direction with respect to the first support.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 28, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Taiki Nonaka, Daiki Nakamura, Nozomu Sugisawa, Kazuhiko Fujita, Shunpei Yamazaki
  • Publication number: 20230380180
    Abstract: A ferroelectric device (100) that includes a metal nitride film (130) with favorable ferroelectricity is provided. The ferroelectric device comprises a first conductor (110), a metal nitride film over the first conductor, a second conductor (120) over the metal nitride film, a first insulator (155) over the second conductor, and a second insulator (152) over the first insulator.
    Type: Application
    Filed: October 12, 2021
    Publication date: November 23, 2023
    Inventors: Shunpei YAMAZAKI, Tomonori NAKAYAMA, Masahiro TAKAHASHI, Hitoshi KUNITAKE
  • Publication number: 20230380175
    Abstract: A semiconductor device that has lower power consumption and is capable of non-destructive reading is provided. The semiconductor device includes first to fourth transistors and first and second FTJ elements. The first FTJ element and the second FTJ element each include an input terminal, a tunnel insulating film, a dielectric, and an output terminal. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor, a gate of the fourth transistor, and the output terminal of the first FTJ element. One of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor, a gate of the third transistor, and the output terminal of the second FTJ element.
    Type: Application
    Filed: October 7, 2021
    Publication date: November 23, 2023
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takayuki IKEDA
  • Publication number: 20230378371
    Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Shunpei YAMAZAKI, Junichi KOEZUKA, Kenichi OKAZAKI, Yukinori SHIMA, Shinpei MATSUDA, Haruyuki BABA, Ryunosuke HONDA
  • Publication number: 20230378459
    Abstract: A lithium-ion secondary battery having high capacity and excellent charge and discharge cycle performance is provided. A secondary battery having high capacity is provided. A secondary battery with excellent charge and discharge characteristics is provided. A secondary battery in which a reduction in capacity is suppressed even when a state being charged with a high voltage is held for a long time is provided. In the secondary battery, after constant current charging is performed in an environment at 60° C. with a current value of 0.5 C until a voltage reaches 4.5 V, a charging process of performing constant voltage charging until a current value reaches 0.2 C and a discharging process of performing constant current discharging with a current value of 0.
    Type: Application
    Filed: October 13, 2021
    Publication date: November 23, 2023
    Inventors: Kazutaka KURIKI, Yumiko YONEDA, Shiori SAGA, Yoshiharu ASADA, Shunpei YAMAZAKI
  • Publication number: 20230378189
    Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 23, 2023
    Inventors: Hidekazu MIYAIRI, Takeshi OSADA, Shunpei YAMAZAKI
  • Patent number: 11823600
    Abstract: A display system and vehicle that have novel structures are provided. The display system includes a display panel, a correction circuit, and a memory circuit. The display panel is flexible. The display panel includes a display region and a non-display region. The memory circuit has a function of storing first data about the display region and second data about the non-display region. The non-display region has a region which overlaps with the display region when the display panel is bent. The correction circuit has a function of generating image data to be written to pixels in the display region on the basis of the first data and the second data.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: November 21, 2023
    Inventors: Shunpei Yamazaki, Yoshiyuki Kurokawa
  • Patent number: 11825665
    Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: November 21, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 11823036
    Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: November 21, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Takayuki Ikeda, Atsuo Isobe, Atsushi Miyaguchi, Shunpei Yamazaki
  • Patent number: 11824124
    Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 21, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 11824068
    Abstract: A display device in which a peripheral circuit portion has high operation stability is provided. The display device includes a first substrate and a second substrate. A first insulating layer is provided over a first surface of the first substrate. A second insulating layer is provided over a first surface of the second substrate. The first surface of the first substrate and the first surface of the second substrate face each other. An adhesive layer is provided between the first insulating layer and the second insulating layer. A protective film in contact with the first substrate, the first insulating layer, the adhesive layer, the second insulating layer, and the second substrate is formed in the vicinity of a peripheral portion of the first substrate and the second substrate.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: November 21, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata, Takashi Hamada, Kohei Yokoyama, Yasuhiro Jinbo, Tetsuji Ishitani, Daisuke Kubota
  • Publication number: 20230369511
    Abstract: A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20230369510
    Abstract: An objet of the present invention is to provide a semiconductor device with a new structure. Disclosed is a semiconductor device including a first transistor which includes a channel formation region on a substrate containing a semiconductor material, impurity regions formed with the channel formation region interposed therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode which are electrically connected to the impurity region; and a second transistor which includes a second gate electrode over the substrate containing a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Keitaro IMAI
  • Publication number: 20230368022
    Abstract: A reduction in concentration due to a change in an emotion is inhibited. A change in an emotion of the human is suitably reduced. Part (in particular, an eye or an eye and its vicinity) or the whole of a user's face is detected, a feature of the user's face is extracted from data on the detected part or whole of the face, and an emotion of the user is estimated from the extracted feature of the face. In the case where the estimated emotion is an emotion that might reduce concentration, for example, a stimulus is applied to the sense of sight, the sense of hearing, the sense of touch, the sense of smell, or the like of the user to recover the concentration of the user.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 16, 2023
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Daisuke KUBOTA, Yoshiaki OIKAWA, Kensuke YOSHIZUMI