Patents by Inventor Shunpei Yamazaki

Shunpei Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11871641
    Abstract: A display device having a function of sensing light is provided. A highly convenient display device is provided. The display device includes a first substrate, a second substrate, a light-receiving element, a transistor, and a light-emitting element in a display portion. The light-receiving element, the transistor, and the light-emitting element are each positioned between the first substrate and the second substrate. The light-receiving element is positioned closer to the first substrate than the transistor is. The light-emitting element is positioned closer to the second substrate than the transistor is. The light-receiving element includes a layer containing an organic compound. The transistor is electrically connected to the light-emitting element. The display device preferably further includes a lens and light transmitted through the lens preferably enters the light-receiving element.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Kubota, Ryo Hatsumi, Taisuke Kamada
  • Patent number: 11869453
    Abstract: To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n?3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: January 9, 2024
    Inventors: Hiroyuki Miyake, Kouhei Toyotaka, Shunpei Yamazaki
  • Patent number: 11869417
    Abstract: The power consumption of a display device is reduced. The power consumption of a driver circuit in a display device is reduced. A pixel included in the display device includes a display element. The pixel is configured to have a function of retaining a first voltage corresponding to a first input pulse signal and a function of driving the display element with a third voltage obtained by addition of a second voltage corresponding to a second input pulse signal to the first voltage.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kei Takahashi, Susumu Kawashima, Koji Kusunoki, Kazunori Watanabe
  • Patent number: 11869981
    Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. One embodiment of the present invention is a semiconductor device which includes a gate electrode, an insulating film over the gate electrode, an oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film include the same element. The second oxide semiconductor film includes a region having lower crystallinity than one or both of the first oxide semiconductor film and the third oxide semiconductor film.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yasutaka Nakazawa
  • Patent number: 11869979
    Abstract: A semiconductor device includes a transistor including, a first to fifth insulator, a first to third oxide, a first to third conductor. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Katsuaki Tochibayashi, Ryota Hodo, Kentaro Sugaya, Naoto Yamade
  • Patent number: 11869977
    Abstract: A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; agate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11868877
    Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Takayuki Ikeda, Atsuo Isobe, Atsushi Miyaguchi, Shunpei Yamazaki
  • Patent number: 11869980
    Abstract: A novel material is provided. A composite oxide semiconductor in which a first region and a plurality of second regions are mixed is provided. Note that the first region contains at least indium, an element M (the element M is one or more of Al, Ga, Y, and Sn), and zinc, and the plurality of second regions contain indium and zinc. Since the plurality of second regions have a higher concentration of indium than the first region, the plurality of second regions have a higher conductivity than the first region. An end portion of one of the plurality of second regions overlaps with an end portion of another one of the plurality of second regions. The plurality of second regions are three-dimensionally surrounded with the first region.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20240006539
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Inventors: Shunpei YAMAZAKI, Hiromi SAWAI, Ryo TOKUMARU, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Sho NAGAMATSU, Tomoaki MORIWAKA
  • Publication number: 20240006418
    Abstract: An object is to provide a highly reliable transistor. In a bottom-gate transistor including an oxide semiconductor layer as a semiconductor layer where a channel is formed, an insulating layer containing excess oxygen is formed over the oxide semiconductor layer, and then an insulating layer through which impurities do not easily pass is formed without exposure to the air. As the insulating layer through which impurities do not easily pass, an aluminum oxide layer or the like can be used. When a conductive layer with a function of absorbing hydrogen is used for a source electrode and a drain electrode, the amount of hydrogen in the oxide semiconductor layer can be reduced.
    Type: Application
    Filed: September 13, 2023
    Publication date: January 4, 2024
    Inventor: Shunpei Yamazaki
  • Publication number: 20240006419
    Abstract: A display device that is suitable for increasing its size is provided.
    Type: Application
    Filed: August 2, 2023
    Publication date: January 4, 2024
    Inventors: Shunpei YAMAZAKI, Kei TAKAHASHI, Yoshiyuki KUROKAWA
  • Publication number: 20240002998
    Abstract: A novel sputtering target is provided. The sputtering target includes a first region and a second region. The first region contains a first metal oxide containing an element M1 (the element M1 is one or more elements selected from Al, Ga, Si, Mg, Zr, and B). The second region contains a second metal oxide containing indium and zinc. The first region and the second region are separated from each other. Each of the first region and the second region is a crystal grain. A crystal grain boundary is observed between the first region and the second region. The diameter of each of the first region and the second region is greater than or equal to 5 nm and less than or equal to 10 ?m.
    Type: Application
    Filed: June 23, 2023
    Publication date: January 4, 2024
    Inventors: Shunpei YAMAZAKI, Yuichi SATO, Fumito ISAKA, Toshikazu OHNO
  • Publication number: 20240004229
    Abstract: A display device including a peripheral circuit portion with high operation stability. The display device includes a first substrate and a second substrate. A first insulating layer is on a first plane of the first substrate, and a second insulating layer is on a first plane of the second substrate. An area of the first plane of the first substrate is the same as an area of the first plane of the second substrate. The first plane of the first substrate and the first plane of the second substrate face each other. A bonding layer is between the first insulating layer and the second insulating layer. A protection film is in contact with the first substrate, the first insulating layer, the bonding layer, the second insulating layer, and the second substrate.
    Type: Application
    Filed: April 21, 2023
    Publication date: January 4, 2024
    Applicant: Semiconductor Energy Laboratory Co, Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu HIRAKATA, Tetsuji ISHITANI, Daisuke KUBOTA, Ryo HATSUMI, Masaru NAKANO, Takashi HAMADA
  • Patent number: 11862649
    Abstract: An imaging device that can obtain imaging data corresponding to high-resolution images in a short period of time is provided. The imaging device includes a pixel including a photoelectric conversion element and n (n is an integer more than 2 inclusive) retention circuits. The photoelectric conversion element and the n retention circuits are stacked. One electrode of the photoelectric conversion element is electrically connected to the first to n-th retention circuits. The retention circuits include OS transistors with an extremely low off-state current feature, and can retain imaging data for a long time. In the first to n-th periods, the imaging device obtains the first to n-th imaging data and retains it in the first to n-th retention circuits. Then, the first to n-th imaging data retained in the first to n-th retention circuits are read out. The read imaging data is output outside the imaging data through AD conversion.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: January 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Hidetomo Kobayashi, Takashi Nakagawa, Yusuke Negoro, Shunpei Yamazaki
  • Patent number: 11862454
    Abstract: A change in electrical characteristics in a semiconductor device including an oxide semiconductor film is inhibited, and the reliability is improved. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, a first metal oxide film over the second insulating film, and a second metal oxide film over the first metal oxide film. The first metal oxide film contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film. The second metal oxide film includes a region where the second metal oxide film and the first metal oxide film are mixed.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: January 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Masami Jintyou
  • Patent number: 11862643
    Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshinari Sasaki, Junichiro Sakata, Masashi Tsubuku
  • Publication number: 20230419891
    Abstract: Provided is a display system with high display quality and high resolution. The display system includes a first layer and a display portion. The display portion is positioned in a region overlapping with the first layer. The first layer includes a semiconductor substrate containing silicon as a material, and a plurality of first transistors and a plurality of second transistors whose channel formation regions contain silicon are formed over the semiconductor substrate. The first layer includes a first circuit and a second circuit; the first circuit includes a driver circuit for driving the display portion; and the second circuit includes a memory device, a GPU, and an EL correction circuit. The display portion includes a pixel, and the pixel includes a light-emitting device containing organic EL and is electrically connected to the driver circuit.
    Type: Application
    Filed: November 26, 2021
    Publication date: December 28, 2023
    Inventors: Shunpei YAMAZAKI, Tatsuya ONUKI, Hajime KIMURA
  • Publication number: 20230422592
    Abstract: Manufacturing equipment of a light-emitting device with which steps from formation to sealing of a light-emitting element can be successively performed is provided. The manufacturing equipment includes a vacuum controlled cluster and an atmosphere controlled cluster and has a function of forming the light-emitting device by forming, over a substrate provided with a first electrode, an island-shaped organic compound over the first electrode, a second electrode over the organic compound, and a protective film over the second electrode through a plurality of film formation steps in the vacuum cluster, a lithography step in the atmosphere controlled cluster, and an etching step in the vacuum cluster.
    Type: Application
    Filed: November 25, 2021
    Publication date: December 28, 2023
    Inventors: Shingo EGUCHI, Hiroki ADACHI, Kenichi OKAZAKI, Naoto KUSUMOTO, Kensuke YOSHIZUMI, Shunpei YAMAZAKI
  • Publication number: 20230420568
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Application
    Filed: September 8, 2023
    Publication date: December 28, 2023
    Inventors: Shunpei YAMAZAKI, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Hideyuki KISHIDA
  • Publication number: 20230420674
    Abstract: Novel graphene is provided. A novel graphene compound is provided. An electrode having a high output is provided. A novel electrode is provided. A secondary battery with little deterioration is provided. A secondary battery with a high degree of safety is provided. Graphene has a vacancy formed with a many-membered ring that is a nine- or more-membered ring composed of carbon atoms. One or more of the carbon atoms included in the many-membered ring are terminated with fluorine.
    Type: Application
    Filed: November 5, 2021
    Publication date: December 28, 2023
    Inventors: Shunpei YAMAZAKI, Kazutaka KURIKI, Taisuke NAKAO, Teruaki OCHIAI