Patents by Inventor Shunsuke ASABA

Shunsuke ASABA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180277634
    Abstract: A semiconductor device of an embodiment includes first and second electrodes, a first gate electrode, a semiconductor layer disposed between the first electrode and a band gap of the semiconductor layer being wider than a band gap of silicon, a silicon layer between the semiconductor layer and the first electrode, a metal layer between the semiconductor layer and the silicon layer, a first semiconductor region of a first-conductivity type in the semiconductor layer, a first silicon region of the first-conductivity type in the silicon layer, a second silicon region of a second-conductivity type in the first silicon region, a third silicon region of the second-conductivity type in the first silicon region and separated from the second silicon region, a first gate insulating layer, a fourth silicon region of the first-conductivity type in the second silicon region, and a fifth silicon region in the third silicon region.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke ASABA, Teruyuki OHASHI
  • Patent number: 10084046
    Abstract: A semiconductor device of an embodiment includes first and second electrodes, a first gate electrode, a semiconductor layer disposed between the first electrode and a band gap of the semiconductor layer being wider than a band gap of silicon, a silicon layer between the semiconductor layer and the first electrode, a metal layer between the semiconductor layer and the silicon layer, a first semiconductor region of a first-conductivity type in the semiconductor layer, a first silicon region of the first-conductivity type in the silicon layer, a second silicon region of a second-conductivity type in the first silicon region, a third silicon region of the second-conductivity type in the first silicon region and separated from the second silicon region, a first gate insulating layer, a fourth silicon region of the first-conductivity type in the second silicon region, and a fifth silicon region in the third silicon region.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Asaba, Teruyuki Ohashi
  • Patent number: 9530767
    Abstract: According to one embodiment, a semiconductor light emitting element includes a base body, first to sixth semiconductor layers, a first conductive layer, and a first pad layer. The first semiconductor layer is separated from the base body and includes first and second semiconductor regions arranged with each other. The second semiconductor layer is provided between the second semiconductor region and the base body. The third semiconductor layer is provided between the second semiconductor region and the second semiconductor layer. The fourth semiconductor layer is separated from the base body, arranged with the first semiconductor layer. The fifth semiconductor layer is provided between the base body and one portion of the fourth semiconductor layer. The sixth semiconductor layer is provided between the fifth semiconductor layer and the one portion. The first conductive layer includes first, second, and third conductive regions. The first pad layer includes a first pad region.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: December 27, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Hiroshi Ono, Shunsuke Asaba, Shinya Nunoue
  • Publication number: 20160284685
    Abstract: According to one embodiment, a semiconductor light emitting element includes a base body, first to sixth semiconductor layers, a first conductive layer, and a first pad layer. The first semiconductor layer is separated from the base body and includes first and second semiconductor regions arranged with each other. The second semiconductor layer is provided between the second semiconductor region and the base body. The third semiconductor layer is provided between the second semiconductor region and the second semiconductor layer. The fourth semiconductor layer is separated from the base body, arranged with the first semiconductor layer. The fifth semiconductor layer is provided between the base body and one portion of the fourth semiconductor layer. The sixth semiconductor layer is provided between the fifth semiconductor layer and the one portion. The first conductive layer includes first, second, and third conductive regions. The first pad layer includes a first pad region.
    Type: Application
    Filed: March 14, 2016
    Publication date: September 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jumpei TAJIMA, Hiroshi ONO, Shunsuke ASABA, Shinya NUNOUE