Abstract: A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.

Abstract: A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.

Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

Abstract: A semiconductor device includes: a semiconductor base; a trench insulating film which is provided on the inner wall surface of a trench formed from the upper surface of the semiconductor base in a film thickness direction of the semiconductor base and including a charged region which is charged positively; and a gate electrode provided on the trench insulating film within the trench. The positive charge density of the charged region at least in a side part of an outer region of the trench insulating film which is provided on the side surface of the trench is higher than that of an inner region of the trench insulating film which is opposite to the outer region, the outer region being in contact with the semiconductor base.

Abstract: A semiconductor device includes: a semiconductor base 10 in which a first trench 101 is formed in a mesh-like shape in a plan view and a second trench 102 is formed in a mesh opening surrounded by the first trench 101; a first semiconductor element 1 which is formed in the semiconductor base 10 and includes a first gate electrode 81 provided within the first trench 101; and a second semiconductor element 2 which is formed in the semiconductor base 10 and includes a second gate electrode 82 provided within the second trench 102 surrounded by the first gate electrode 81.

Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

Abstract: A semiconductor device in embodiments, may include a device region having: two active trenches, each having at least a gate electrode. Two insulated trenches each having an electrode may be formed between the two active trenches separated by a junction. First p-doped layers may be provided between a first active trench and a first insulated trench, and between a second active trenches and a second insulated trench. Second p-doped layers may be provided between a first insulated trench and a second insulated trench with the junction arranged therebetween. The second p-doped layers may be provided on an external surface of the respective first one and second one of the two insulated trenches at a depth and a thickness set to form a current path when the power semiconductor device is in an OFF state.

Abstract: A semiconductor device includes: a semiconductor base; a trench insulating film 50 which is provided on the inner wall surface of a trench formed from the upper surface of the semiconductor base in the film thickness direction and includes a charged region which is charged positively; and a gate electrode 80 provided on the trench insulating film 50 within the trench. The positive charge density of the charged region at least in a side part of an outer region of the trench insulating film 50 which is provided on the side surface of the trench is higher than that of an inner region of the trench insulating film which is opposite to the outer region, the outer region being in contact with the semiconductor base.

Abstract: A semiconductor device includes: a semiconductor base 10 in which a first trench 101 is formed in a mesh-like shape in a plan view and a second trench 102 is formed in a mesh opening surrounded by the first trench 101; a first semiconductor element 1 which is formed in the semiconductor base 10 and includes a first gate electrode 81 provided within the first trench 101; and a second semiconductor element 2 which is formed in the semiconductor base 10 and includes a second gate electrode 82 provided within the second trench 102 surrounded by the first gate electrode 81.

Abstract: A semiconductor device may comprise a substrate; a trench formed in the substrate and filled with an insulating layer; and a gate electrode and a source embedded in the insulating layer. The gate electrode and the source electrode may be positioned in the insulating layer in the trench above and below each other. From a cross-sectional perspective, the gate electrode and the source electrode are not overlapped in horizontal or vertical direction. The trench may extend to a first depth of a bottom surface of the trench below the gate electrode, and may extend to a second depth of the bottom surface of the trench below the source electrode. The first depth and the second depth may be different.

Abstract: A semiconductor device may include a device region having one or more active trenches, a field termination region having an edge trench. A depth of the edge trench is larger than a depth of the one or more active trenches. A thickness of an insulation layer in the edge trench is larger than a thickness of an insulation layer in the one or more active trenches. In some embodiments, the first depth is from 1.2 to 2.0 times larger than the second depth, and a first width of the edge trench is 1.5 to 4.0 times larger than a second width of the one or more active trenches. In a cross-sectional view, a gate electrode of the edge trench is laterally offset from the source electrode in a depth direction of the edge trench such that the gate electrode and the source electrode do not overlap.

Abstract: A semiconductor device may comprise a substrate; a trench formed in the substrate and filled with an insulating layer; and a gate electrode and a source embedded in the insulating layer. The gate electrode and the source electrode may be positioned in the insulating layer in the trench above and below each other. From a cross-sectional perspective, the gate electrode and the source electrode are not overlapped in horizontal or vertical direction. The trench may extend to a first depth of a bottom surface of the trench below the gate electrode, and may extend to a second depth of the bottom surface of the trench below the source electrode. The first depth and the second depth may be different.

Abstract: A semiconductor device has a through hole penetrating a substrate, an insulating film filling the through hole, a gate electrode and a source electrode. The through hole penetrates a substrate on a first side. A first gate electrode may be embedded in the insulating film. A first source electrode may be embedded in the insulating film deeper than the first gate electrode. A first width of the first opening may be larger than a second width of an internal portion of the through hole. A ratio may be established between the first width and the second width. A second source electrode may be embedded in the insulating film deeper than the first source electrode. A second gate electrode may be embedded deeper than the second source electrode in a vertical direction within the through hole. The first opening and the second opening may be laterally offset.

Abstract: A semiconductor device that includes a semiconductor substrate; a trench in the semiconductor substrate; a gate electrode in the trench; a source electrode in the trench, the source electrode being disposed between the gate electrode and a bottom wall of the trench; a partitioning layer in the trench, the partitioning layer extending between the gate electrode and the source electrode; and an insulating film in the trench.

Abstract: A semiconductor device includes: three or more transistors, which are formed on a semiconductor substrate and arranged in one direction; and a PN junction diode, which is formed in a part of a region between the transistors, wherein each of the transistors includes: a trench: a conductive region; and an insulating film, wherein a first thickness of a first insulating film is a thickness between an end portion of a first conductive region on a bottom surface side of the first trench and a bottom surface of the first trench, wherein a second thickness of a second insulating film is a thickness between an end portion of a second conductive region on a bottom surface side of the second trench and a bottom surface of the second trench and wherein the first thickness is thicker than the second thickness.

Abstract: One or more embodiments disclose a semiconductor device that includes a trench extending into a drift zone of a semiconductor body from a surface of the semiconductor body in a first direction; a dielectric structure in the trench; a gate electrode in the dielectric structure; a body region of a first conductivity type other than a second conductivity type of the drift zone; and an auxiliary structure of the second conductivity type adjoining the drift zone, the body region and the dielectric structure, wherein the auxiliary structure extends outwardly from the trench in a second direction, the second direction orthogonal to the first direction, and in the second direction, a first length of the auxiliary structure is larger than a second length of the trench.

Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

Abstract: A semiconductor device includes: three or more transistors, which are formed on a semiconductor substrate and arranged in one direction; and a PN junction diode, which is formed in a part of a region between the transistors, wherein the transistor includes: a trench, which is formed inwardly from a front surface; and a conductive region in the trench; wherein a first trench is a trench of the transistor which is not adjacent to the PN junction diode, and a second trench is a trench of one or both of the two transistors adjacent to the PN junction diode, wherein a bottom surface of the first trench is formed in a semiconductor region of a first impurity concentration, and wherein a bottom surface of the second trench is formed in a semiconductor region of a second impurity concentration, which is higher than the first impurity concentration.

Abstract: A semiconductor device has a plurality of transistors, which have first electrodes in first trenches, and includes: two second trenches, which are formed side by side between the first trenches. A second electrode is formed in each of the two second trenches. A first impurity region is formed between the first trench and the second trench; a second impurity region is formed to abut on the first trench; a third impurity region is formed to abut on the second trench; a fourth impurity region, which is formed between two of the second trenches and has a higher impurity concentration than the first impurity region; and a fifth impurity region is formed below the first impurity region and the fourth impurity region. A third electrode is formed to be electrically connected to the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region.