Abstract: A semiconductor device includes: a trench; a first electrode is formed in the trench; a first impurity region, which has a first conductivity type and is formed to abut on the trench; a second impurity region, which has a second conductivity type and is formed to abut the trench; an insulating film, which is formed on the front surface of the semiconductor substrate; a conductive plug, which is formed to penetrate through the insulating film and is electrically connected to the first impurity region and the second impurity region; wherein the conductive plug includes: a silicon layer made of silicon other than a single crystal; a silicide crystallite contained in the silicon layer; and a blocking layer that is formed to cover sides of the silicon layer and is made of a material that is impervious to the silicide crystallites.

Abstract: Semiconductor power devices such as vertical FPMOS are described having a plurality of trenches formed at a top portion of a semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction. Each trench has sidewalls generally perpendicular to a longitudinal direction of the trench and extending downward from a top surface to a trench bottom. Gate electrodes and source electrodes are positioned in the trenches. Higher voltage resistance is achieved while increasing current by spacing the trenches and providing particular dopant levels to allow more even distribution of depletion layer regions across a power device during use.

Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

Abstract: Semiconductor power devices such as vertical FPMOS are described preferably having a plurality of trenches formed at a top portion of a semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction. Each trench has sidewalls generally perpendicular to a longitudinal direction of the trench and extending downward from a top surface to a trench bottom. Gate electrodes and source electrodes are positioned in the trenches with controlled spacing between their surfaces to achieve increased capacitance between them at increasing depth from the top surface. This provides higher frequency performance at higher power levels while improving tolerance to higher voltage.