Patents by Inventor Shunsuke Hayashi
Shunsuke Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110062943Abstract: A timing detection device includes a draw back amount acquiring unit and a detecting unit. The draw back amount acquiring unit is configured to acquire a draw back amount of a received signal with respect to a peak value of the signal. The detecting unit is configured to detect the timing at which the draw back amount acquired by the draw back amount acquiring unit has exceeded a constant value as the timing at which a value of the signal is switched.Type: ApplicationFiled: September 15, 2010Publication date: March 17, 2011Applicant: YOKOGAWA ELECTRIC CORPORATIONInventors: Noriaki Kihara, Shunsuke Hayashi, Kenji Habaguchi, Takayuki Ooshima
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Patent number: 7806396Abstract: A paper note handling apparatus includes a pay-in and pay-out mouth through which a paper note is paid in or paid out, a conveyance for conveying the paper note, a discrimination part to discriminate authenticity and denomination of the conveyed paper note, a temporary hold part to temporarily hold the paper note, a storing part to store the paper note, and a shifter to shift a position of the paper note in a widthwise direction of conveyance. The shifter rotates in a direction inclined relative to a direction of conveyance of the paper note and comes into contact with the paper note to shift the position of the paper note in the widthwise direction of conveyance.Type: GrantFiled: June 17, 2008Date of Patent: October 5, 2010Assignee: Hitachi-Omron Terminal Solutions, Corp.Inventors: Shunsuke Hayashi, Masahiro Seguchi, Masayasu Ueno, Hidetoshi Hata, Hisanori Takemura, Junji Nishiwaki
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Patent number: 7733321Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.Type: GrantFiled: October 5, 2006Date of Patent: June 8, 2010Assignee: Sharp Kabushiki KaishaInventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
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Patent number: 7688302Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.Type: GrantFiled: October 5, 2006Date of Patent: March 30, 2010Assignee: Sharp Kabushiki KaishaInventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
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Patent number: 7648138Abstract: A sheet handling apparatus is proposed to be able to stably shift a position of a sheet.Type: GrantFiled: September 12, 2005Date of Patent: January 19, 2010Assignee: Hitachi-Omron Terminal Solutions, Corp.Inventors: Shunsuke Hayashi, Masahiro Seguchi, Masayasu Ueno, Hidetoshi Hata, Hisanori Takemura, Junji Nishiwaki
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Publication number: 20090278948Abstract: A method of presenting information, capable of displaying an image including one or more objects being in the vicinity of the ground, the method including the steps of: acquiring viewpoint information; acquiring visual line information; acquiring posture information; acquiring additional information related to the object position information; calculating horizon line information in the image; determining a reference line on the image on the basis of the horizon line information and the posture information; calculating distance information from the viewpoint position to the object; determining a display attribute of the additional information including a display mode of the additional information and a display position of the additional information in the image with respect to the reference line; and presenting the additional information on the basis of the display mode so as to reveal a relationship between the additional information and the object when displaying the image on the display unit.Type: ApplicationFiled: March 27, 2009Publication date: November 12, 2009Applicant: Sony CorporationInventor: Shunsuke HAYASHI
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Publication number: 20090013102Abstract: A communication system has: a controller that is connected to a plurality of field devices for inputting and outputting an analog signal and a digital signal; and a system computer that is provided in an upper hierarchical layer of the controller, and communicates with one of the plurality of field devices by using the digital signal through the controller. The communication system further has a path establishing section that selects a field device for communication from the plural field devices, and establishes a virtual communication channel to be a communication path for performing one-to-one communication with the selected field device via the system computer and the controller.Type: ApplicationFiled: July 20, 2005Publication date: January 8, 2009Inventor: Shunsuke Hayashi
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Publication number: 20080251349Abstract: A paper note handling apparatus includes a pay-in and pay-out mouth through which a paper note is paid in or paid out, a conveyance for conveying the paper note, a discrimination part to discriminate authenticity and denomination of the conveyed paper note, a temporary hold part to temporarily hold the paper note, a storing part to store the paper note, and a shifter to shift a position of the paper note in a widthwise direction of conveyance. The shifter rotates in a direction inclined relative to a direction of conveyance of the paper note and comes into contact with the paper note to shift the position of the paper note in the widthwise direction of conveyance.Type: ApplicationFiled: June 17, 2008Publication date: October 16, 2008Inventors: Shunsuke Hayashi, Masahiro Seguchi, Masayasu Ueno, Hidetoshi Hata, Hisanori Takemura, Junji Nishiwaki
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Patent number: 7384037Abstract: A sheet housing part of a sheet handling machine is provided with a guide member for adjusting a size of a housing space of the sheet housing part. A tip end part of the guide member is made pivotable, and is provided with a biasing member for swinging the tip end part in a direction of a side wall of the sheet housing part. A gap provided between the guide member and an inner wall of the sheet housing part is closed with this construction, and thereby, a foreign matter is prevented from entering this gap.Type: GrantFiled: March 1, 2005Date of Patent: June 10, 2008Assignee: Hitachi-Omron Terminal Solutions, Corp.Inventors: Hideyuki Sawayama, Daisuke Tokunaga, Shunsuke Hayashi, Sho Mizuno
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Patent number: 7289097Abstract: The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.Type: GrantFiled: November 6, 2003Date of Patent: October 30, 2007Assignee: Sharp Kabushiki KaishaInventors: Seijirou Gyouten, Sachio Tsujino, Hajime Washio, Eiji Matsuda, Keiichi Ina, Yuhichiroh Murakami, Shunsuke Hayashi, Mamoru Onda
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Publication number: 20070242021Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.Type: ApplicationFiled: June 19, 2007Publication date: October 18, 2007Inventors: Yuhichiroh Murakami, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Shunsuke Hayashi
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Patent number: 7274351Abstract: A driver circuit for a display device includes a plurality of set-reset flip-flops and switch circuits, and is arranged so that a timing pulse for sampling outputted from the flip-flop is supplied to the switch circuit, so as to cause the switch circuit to receive a clock signal. The clock signal operates as a set signal of the next stage flip-flop and outputted as a control signal for carrying out pre-charging of a data signal line and a selected pixel connected to the data signal line, with a switch. Thus, in case of performing pre-charging of a signal supplying line with an internal pre-charging circuit by using a pre-charging power source having small driving ability, this arrangement can provide a driver circuit for a display device capable of preventing fluctuation of a signal supplied to a different signal supplying line, while keeping the circuit scale of the shift register small.Type: GrantFiled: May 28, 2003Date of Patent: September 25, 2007Assignee: Sharp Kabushiki KaishaInventors: Hajime Washio, Shunsuke Hayashi
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Patent number: 7248243Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.Type: GrantFiled: May 16, 2003Date of Patent: July 24, 2007Assignee: Sharp Kabushiki KaishaInventors: Yuhichiroh Murakami, Seijirou Gyouten, Shunsuke Hayashi, Hajime Washio, Eiji Matsuda, Sachio Tsujino
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Publication number: 20070024567Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.Type: ApplicationFiled: October 5, 2006Publication date: February 1, 2007Applicant: Sharp Kabushiki KaishaInventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
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Publication number: 20070024568Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.Type: ApplicationFiled: October 5, 2006Publication date: February 1, 2007Applicant: Sharp Kabushiki KaishaInventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
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Patent number: 7133017Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.Type: GrantFiled: March 14, 2003Date of Patent: November 7, 2006Assignee: Sharp Kabushiki KaishaInventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
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Publication number: 20060070840Abstract: A sheet handling apparatus is proposed to be able to stably shift a position of a sheet.Type: ApplicationFiled: September 12, 2005Publication date: April 6, 2006Inventors: Shunsuke Hayashi, Masahiro Seguchi, Masayasu Ueno, Hidetoshi Hata, Hisanori Takemura, Junji Nishiwaki
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Patent number: 6996203Abstract: The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct signal; a waveform change section for changing in waveform a signal output of one of the flip-flops which is in a first predetermined stage; and an inspection signal switching section for switching, in accordance with the direction instruct signal, an output between the signal output which has been changed in waveform in the waveform change section and a signal output of one of the flip-flops which is in a second predetermined stage.Type: GrantFiled: June 4, 2004Date of Patent: February 7, 2006Assignee: Sharp Kabushiki KaishaInventors: Mamoru Onda, Hajime Washio, Shunsuke Hayashi, Hiroshi Murofushi, Nobuhiko Suzuki
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Patent number: 6973103Abstract: A communication control system and method comprising, in one embodiment, a plurality of strobe signals are generated at different timings in a transmission circuit and a plurality of latch circuits equal to the number of strobe signals are provided in a receiver circuit so that data is retained in each latch circuit using the strobe signals one at a time.Type: GrantFiled: September 23, 2002Date of Patent: December 6, 2005Assignee: Yokogawa Electric CorporationInventors: Shunsuke Hayashi, Hideo Matsukawa, Toyoaki Yokoi
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Patent number: 6952404Abstract: A communication control system and method comprising, in one embodiment, a master station connected to a slave station using two redundant buses, wherein command frames having the same content are sent out to the buses and the communication process is changed depending on whether or not the contents of the command frames, when received by the receiving station, are identical.Type: GrantFiled: November 4, 2002Date of Patent: October 4, 2005Assignee: Yokogawa Electric CorporationInventors: Shunsuke Hayashi, Hideo Matsukawa, Toyoaki Yokoi