Abstract: A sheet housing part of a sheet handling machine is provided with a guide member for adjusting a size of a housing space of the sheet housing part. A tip end part of the guide member is made pivotable, and is provided with a biasing member for swinging the tip end part in a direction of a side wall of the sheet housing part. A gap provided between the guide member and an inner wall of the sheet housing part is closed with this construction, and thereby, a foreign matter is prevented from entering this gap.

Abstract: The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct signal; a waveform change section for changing in waveform a signal output of one of the flip-flops which is in a first predetermined stage; and an inspection signal switching section for switching, in accordance with the direction instruct signal, an output between the signal output which has been changed in waveform in the waveform change section and a signal output of one of the flip-flops which is in a second predetermined stage.

Abstract: The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.

Abstract: A driver circuit for a display device includes a plurality of set-reset flip-flops and switch circuits, and is arranged so that a timing pulse for sampling outputted from the flip-flop is supplied to the switch circuit, so as to cause the switch circuit to receive a clock signal. The clock signal operates as a set signal of the next stage flip-flop and outputted as a control signal for carrying out pre-charging of a data signal line and a selected pixel connected to the data signal line, with a switch. Thus, in case of performing pre-charging of a signal supplying line with an internal pre-charging circuit by using a pre-charging power source having small driving ability, this arrangement can provide a driver circuit for a display device capable of preventing fluctuation of a signal supplied to a different signal supplying line, while keeping the circuit scale of the shift register small.

Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: A communication control system and method comprising, in one embodiment, a master station connected to a slave station using two redundant buses, wherein command frames having the same content are sent out to the buses and the communication process is changed depending on whether or not the contents of the command frames, when received by the a receiving station, are identical. In another embodiment, a plurality of units are connected to each bus in a multi-drop configuration, and a line length of each bus is defined so that reflected signals from other units reach a receiving unit on each bus after the transition period of a received signal at that receiving unit ends. In still another embodiment, a unit is connected to each bus and the unit is provided with a driver IC, wherein transmission data is first encoded into bit signals having a fixed number of bits, then the signals are supplied to the driver IC.

Abstract: A communication control system and method comprising, in one embodiment, a master station connected to a slave station using two redundant buses, wherein command frames having the same content are sent out to the buses and the communication process is changed depending on whether or not the contents of the command frames, when received by the a receiving station, are identical. In another embodiment, a plurality of units are connected to each bus in a multi-drop configuration, and a line length of each bus is defined so that reflected signals from other units reach a receiving unit on each bus after the transition period of a received signal at that receiving unit ends. In still another embodiment, a unit is connected to each bus and the unit is provided with a driver IC, wherein transmission data is first encoded into bit signals having a fixed number of bits, then the signals are supplied to the driver IC.

Abstract: A communication control system and method comprising, in one embodiment, a plurality of strobe signals are generated at different timings in a transmission circuit and a plurality of latch circuits equal to the number of strobe signals are provided in a receiver circuit so that data is retained in each latch circuit using the strobe signals one at a time.

Abstract: A method for whitening teeth with a neat finishing, and a considerable durability can be provided at a low cost. Further, a method for easily making up nails can be provided. An apparatus of the present invention comprises a lower mold base for placing a male mold of a tooth form or a nail form to be attached with the seal, a sheet base for positioning a high polymer material sheet above the lower base, a holder portion for holding a female mold corresponding to the male mold, and a press mechanism for compressing the male mold, the high polymer material sheet placed on the sheet base, and the female mold with each other.

Abstract: Herein disclosed is a duplex computer system to be used in process automations or factory automations. The system is constructed of two computer (or processor) systems connected with a common backplane bus and a plurality of I/O units to be controlled by those computer systems. Each of these systems is composed of a CPU having a self-diagnosis function for outputting a ready signal indicating whether or not its operations can be normally accomplished, a communication interface unit for interfacing with the backplane bus, and a duplex control unit that receives the ready signal output from the CPU in order to determine which of the computer systems is to be brought into a control status while the other is brought into a standby status.

Abstract: A dual computer system comprising a pair of processor units, and a dual control unit for controlling which of the two processor units are to be kept operating or on standby in case of failure of the operated unit; wherein the dual control unit controls which processor unit is to be operated through monitoring of the operating states of the two processor units, and comprising two independent interruption devices for indicating the switching of the two processor units through interruption. The system is effective in improving the continuity of the control at the time of switching.

Abstract: A switching power supply comprising a converting circuit; an analog-to-digital converter for converting a signal referring to an output signal from the converting circuit into digital form; a parallel-to-series converter for converting a bit train signal containing the output signal from the analog-to-digital converter into a pulse train; an isolation means for transmitting the pulse train to the primary winding of a transformer while concurrently electrically isolating the pulse train; a series-to-parallel converter for demodulating the pulse train into a parallel signal; and a control circuit. The converting circuit has a switching device which turns ON and OFF the voltage applied across the primary winding. The converting circuit provides rectification and smoothing of voltage induced in the secondary winding of the transformer, and supplies an output DC voltage to a load.

Abstract: A signal conditioner comprising a receiving part, a transmitting part, and a power supply part, wherein the main functions of these components are digitalized and common circuit elements are used for different functions. Signal conditions may be of several different types, each of which is a hardware which can accommodate various transmitters and actuators.