Abstract: In an SRAM circuit mounted in a semiconductor device, power supply voltage reduction circuits generate reduction voltage obtained by reducing an external power supply voltage. A first power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a drive voltage supplied to a word line driver. A second power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a voltage of a power supply line supplying an operating voltage to a memory cell.

Abstract: Provided is a technology capable of initializing data in memory cells at a relatively high speed while suppressing an area increase. Based on a fact that the reset signal is turned to a high level, a control circuit of a semiconductor device turns a first transistor to an OFF state, a plurality of word lines to a selection state, a precharge circuit to the OFF state, column switches for writing to an ON state, and column switches for reading to the OFF state, causes write circuits to turn first bit lines and second bit lines to a low level and a high level, respectively, and initializes a plurality of memory cells.

Abstract: A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.

Abstract: A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.

Abstract: The control circuit of the semiconductor device initializes a plurality of memory cells. The method is that when the reset signal is at a high level, the control circuit turns off the first transistor, selects multiple word lines, turns off the precharge circuit, turns on the write column switch, and turns off the read column switch. Then, the control circuit initializes a plurality of memory cells by setting the first bit line to the low level and the second bit line to the high level by the writing circuit.

Abstract: A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.

Abstract: A semiconductor device includes: a plurality of P-channel type MOS transistors each whose source-drain path being coupled between a first wiring to which a power supply potential is to be supplied and a power supply node included in a logic circuit block, and a plurality of N-channel type MOS transistors each whose source-drain path being coupled between a ground node included in the logic circuit block and a second wiring to which a ground potential is to be supplied. Also, during standby state, each of the plurality of P-channel type MOS transistors and the plurality of N-channel type MOS transistors is diode-connected. According to the above semiconductor device, the current consumption of a logic circuit included in the logic circuit block during standby state can be reduced, and the logic circuit can be returned from standby state to normal operation state in a short time.

Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.

Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: Disclosed is a memory circuit that includes a plurality of columns of bit line pairs, each bit line pair including True and Bar bit lines, between which at least a memory cell is connected; a sense amplifier that has True and Bar terminals and that performs differential amplification; and a switching circuit that selects one of: a straight connection in which the True and Bar bit lines of a selected column bit line pair are connected to the True and Bar terminals of the sense amplifier, respectively; and a cross connection in which the True and Bar bit lines of a selected column bit line pair are connected to the Bar and True terminals of the sense amplifier, respectively.

Abstract: Disclosed is a semiconductor memory device in which a cell is connected to word lines of at least first and second ports, and control of timing of activation of the word lines of the first and second ports is performed based upon first and second clock signals, respectively, comprising first and second test control signals in correspondence with the first and second clock signals that control the respective timings of activation of the word lines of the first and second ports. With regard to the cell with the first and second ports being selected, when the first test control signal is in an activated state and the second test control signal is in a deactivated state, control is exercised so as to mask the second clock signal and, responsive to the first clock signal, activate the first and second word lines simultaneously.

Abstract: A gas sensor includes a sensing element having an electrode pad a metal terminal, and a separator that has insertion holes in which the metal terminal is held. The metal terminal includes a main body and an elastic portion that is integrally connected to the main body and is elastically connected to the electrode pad at a predetermined contact point. The main body includes a front-end-side restricting portion and a rear-end-side restricting portion that restrict the movement of the main body by contacting wall surfaces of the insertion hole when the main body moves in a direction intersecting the direction of an axial line. The contact point is located between the front-end-side restricting portion and the rear-end-side restricting portion in the direction of the axial line. The front-end-side restricting portion and the rear-end-side restricting portion are connected to each other so that a flat board portion is interposed therebetween.