Abstract: Disclosed is a memory circuit that includes a plurality of columns of bit line pairs, each bit line pair including True and Bar bit lines, between which at least a memory cell is connected; a sense amplifier that has True and Bar terminals and that performs differential amplification; and a switching circuit that selects one of: a straight connection in which the True and Bar bit lines of a selected column bit line pair are connected to the True and Bar terminals of the sense amplifier, respectively; and a cross connection in which the True and Bar bit lines of a selected column bit line pair are connected to the Bar and True terminals of the sense amplifier, respectively.

Abstract: There is disclosed a semiconductor memory device in which, activation timing control of a plurality of word lines of a plurality of ports is managed based on a plurality of clock signals, test signals are provided in association with the plurality of clock signals respectively controlling the activation timings of the word lines of the plurality of ports. If, with the cell, with the plurality of ports selected, the one test signal is in an activated state and the other test signal is in a non-activated state, activation of word lines of the plurality of ports is controlled in response to one clock signal, with the other clock signal being then masked. The timing difference, inclusive of the zero timing difference, between the activation timing of the plurality of word lines of the plurality of port may be finely adjusted by a delay control signal.

Abstract: Disclosed is a semiconductor memory device in which a cell is connected to word lines of at least first and second ports, and control of timing of activation of the word lines of the first and second ports is performed based upon first and second clock signals, respectively, comprising first and second test control signals in correspondence with the first and second clock signals that control the respective timings of activation of the word lines of the first and second ports. With regard to the cell with the first and second ports being selected, when the first test control signal is in an activated state and the second test control signal is in a deactivated state, control is exercised so as to mask the second clock signal and, responsive to the first clock signal, activate the first and second word lines simultaneously.

Abstract: A controller arranges macrocells having power terminals and ground terminals in desired positions on a semiconductor chip. The power terminals and ground terminals are arranged in a fourth line layer such that the centers of square power terminals and ground terminals substantially coincide with lattice points, and terminals of different types are not mixed along the same row, for example. The controller then forms an orbital power ring, performs terminal processing of the chip internal power line, retrieves from the terminal information library the defined position of a single terminal in each row from among the power terminals and ground terminals, and identifies the position as that of a terminal to be connected.

Abstract: A controller arranges macrocells having power terminals and ground terminals in desired positions on a semiconductor chip. The power terminals and ground terminals are arranged in a fourth line layer such that the centers of square power terminals and ground terminals substantially coincide with lattice points, and terminals of different types are not mixed along the same row, for example. The controller then forms an orbital power ring, performs terminal processing of the chip internal power line, retrieves from the terminal information library the defined position of a single terminal in each row from among the power terminals and ground terminals, and identifies the position as that of a terminal to be connected.