Abstract: A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.

Abstract: A driving method and device for a shift register. In a data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; in a data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, controlling the cascade signal end to output a fixed voltage signal having a second level.

Abstract: A system and a method for characterizing a target analyte are provided. The system comprises a nanopore and a polymer strand comprising a tether site and a reaction section, wherein the polymer strand is tethered via the tether site so that the polymer strand cannot pass through the nanopore, and wherein the reaction section comprises at least one sensing module which can interact with single molecule of the target analyte.

Abstract: A stretchable pixel array substrate includes a base, pixel structures, and a wiring. The base has first regions and a second region. The pixel structures are respectively disposed on the first regions of the base. The wiring is disposed on the second region of the base. Curved segments of the wiring include a first curved segment and a second curved segment. One of the pixel structures is disposed on one of the first regions. The first curved segment is disposed between the one of the pixel structures and the second curved segment. A distance A exists between a first curved portion and a second curved portion of the first curved segment in a first direction, a distance B exists between a first curved portion and a second curved portion of the second curved segment in the first direction, and A>B.

Abstract: A thin film transistor includes a semiconductor layer, a first gate electrode disposed at one side of the semiconductor layer, a first gate insulating layer disposed between the first gate electrode and the semiconductor layer, a second gate electrode and a third gate electrode disposed at another side of the semiconductor layer, and a second gate insulating layer. The second gate electrode is separated from the third gate electrode. The second gate insulating layer is disposed between the second and third gate electrodes and the semiconductor layer. An orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the second gate electrode on the semiconductor layer. The orthogonal projection of the first gate electrode on the semiconductor layer is partially overlapped with an orthogonal projection of the third gate electrode on the semiconductor layer.

Abstract: A scam detection system includes a user computer that runs a security application and a backend system that runs a scam detector. An email is received at the user computer. The security application extracts and forwards a content of the email, which includes a body of the email, to the backend system. The email body of the email is anonymized by removing personally identifiable information from the email body. A hash of the anonymized email body is generated and compared against hashes of a whitelist and a blacklist. The anonymized email body is classified. A segment of text of the anonymized email body is identified and provided to the user computer when the anonymized email body is classified as scam.

Abstract: A stretchable electronic device includes a substrate, a plurality of electronic elements, and a conductive wiring. The electronic elements and the conductive wiring are disposed on the substrate, and the conductive wiring is electrically connected to the electronic elements. The conductive wiring is formed by stacking an elastic conductive layer and a non-elastic conductive layer. A fracture strain of the elastic conductive layer is greater than a fracture strain of the non-elastic conductive layer, and the non-elastic conductive layer includes a plurality of first fragments which are separated from one another.

Abstract: A machine learning device that performs machine learning of a welding condition for manufacturing an additively-manufactured object by welding a filler metal and depositing weld beads, the machine learning device includes: at least one hardware processor configured to perform a learning process for generating a learned model using two pieces of shape data of a weld bead or a difference between the two pieces of shape data is used as input data and a difference between welding conditions corresponding to the difference between the two pieces of shape data as output data.

Abstract: A method for manufacturing an additively-manufactured object includes forming a plurality of weld beads obtained by melting and solidifying a filler metal sent out from a torch and depositing each weld bead. The method includes forming and depositing a first weld bead of the plurality of weld beads in a first welding control mode, and forming and depositing a second weld bead of the plurality of weld beads in a second welding control mode with a higher heat input than in the first welding control mode. The first welding control mode is a forward and reverse feeding control in which, while the filler metal is fed sequentially in a forward direction and a reverse direction, a current waveform of a power supplied to the filler metal from a power source is synchronized with the forward and reverse feeding of the filler metal.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: A machine learning device that performs machine learning of a welding condition for manufacturing an additively-manufactured object by welding a filler metal and depositing weld beads, the machine learning device includes: at least one hardware processor configured to perform a learning process for generating a learned model using a welding condition of a weld bead and a block pattern formed by the weld bead as input data and shape data of the weld bead as output data.

Abstract: The invention relates to a method for detection of analyte interaction with a channel molecule held in a membrane, comprising the optical detection of a modification in the flux of a signal molecule as it passes through the channel molecule by the action of a membrane potential, wherein the modification in the flux is caused by at least partial blockage of the channel molecule by the analyte. The invention further relates to bilayer arrays, components, methods of manufacture and use.

Abstract: Provided are a mask, a sample collecting tube, and a pathogen collecting apparatus. The mask includes a mask body, a breather valve fixed on the mask body, and a sampling structure including a pathogen adsorption portion. The pathogen adsorption portion is disposed on an inner side of the breather valve and is adapted to adsorb pathogens in exhaled gas. The pathogen adsorption portion is adapted to enter the sample collecting tube to be in contact with a sample preservation solution in the sample collecting tube.

Abstract: A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a substrate, a semiconductor structure, a gate dielectric layer, and a first gate. The semiconductor structure is disposed above the substrate and includes two thick portions and a thin portion located between the two thick portions. A thickness of the two thick portions is larger than a thickness of the thin portion. The gate dielectric layer is disposed on the semiconductor structure. The first gate is disposed on the gate dielectric layer. A width of the first gate is smaller or equal to a width of the thin portion, and the first gate is overlapped with the thin portion in a normal direction of a top surface of the substrate. A doping concentration of the two portions is larger than a doping concentration of the thin portion.

Abstract: An active device substrate includes a substrate, a first semiconductor device and a second semiconductor device. The first semiconductor device and the second semiconductor device are disposed above the substrate. The first semiconductor device includes a first gate, a first semiconductor layer, a first source and a first drain. A first gate dielectric structure is sandwiched between the first gate and the first semiconductor layer. The first gate dielectric structure includes a stack of a portion of a gate dielectric layer and a portion of a ferroelectric material layer. The second semiconductor device is electrically connected to the first semiconductor device and includes a second gate, a second semiconductor layer, a second source and a second drain. Another part of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer.

Abstract: An active device substrate includes a substrate, a first thin film transistor located above the substrate and a second thin film transistor located above the substrate. The first thin film transistor includes a first metal oxide layer, a first gate, a first source and a first drain. A first gate dielectric layer and a second gate dielectric layer are located between the first gate and the first metal oxide layer. The second thin film transistor includes a second metal oxide layer, a second gate, a second source and a second drain. The second gate dielectric layer is located between the second gate and the second metal oxide layer, and the second metal oxide layer is located between the first gate dielectric layer and the second gate dielectric layer. The first gate and the second gate belong to a same patterned layer.

Abstract: A semiconductor device and its manufacturing method are provided. The semiconductor device includes a substrate, an oxygen-containing protrusive structure disposed above the substrate, a metal oxide layer, a gate dielectric layer disposed on the metal oxide layer, and a gate disposed on the gate dielectric layer. The oxygen-containing protrusive structure has a first surface, a second surface opposite to the first surface, and sidewalls connected to the first and second surfaces. The metal oxide layer includes first, second, and third portions. The first portion covers the first surface. The second portion is connected to the first portion and covers the sidewalls of the oxygen-containing protrusive structure. A resistivity of the second portion gradually decreases away from the first portion. The third portion is connected to the second portion and extends from the sidewalls of the oxygen-containing protrusive structure in a direction away from the oxygen-containing protrusive structure.

Abstract: A semiconductor device, including a substrate, a semiconductor structure, a first gate dielectric layer, a first gate, a source, and a drain, is provided. The semiconductor structure includes a first metal oxide layer and a second metal oxide layer. The second metal oxide layer covers a top surface and a sidewall of the first metal oxide layer. The second metal oxide layer has a stepped structure at the sidewall of the first metal oxide layer. A carrier mobility of the first metal oxide layer is greater than a carrier mobility of a channel region of the second metal oxide layer. A thickness of the second metal oxide layer is greater than or equal to a thickness of the first metal oxide layer. A difference between a width of the first gate and a width of the first metal oxide layer is less than 0.5 ?m.

Abstract: A semiconductor device includes a substrate, a semiconductor structure, a gate dielectric layer, a first gate, a source and a drain. The semiconductor structure is disposed above the substrate. The semiconductor structure includes a first thick portion, a second thick portion, and a thin portion between the first thick portion and the second thick portion. The gate dielectric layer is disposed on the semiconductor structure. The first gate is disposed on the gate dielectric layer. The first gate overlaps a portion of the first thick portion and a portion of the thin portion. The first gate does not overlap another portion of the thin portion and the second thick portion. The source is electrically connected to the first thick portion. The drain is electrically connected to the second thick portion.

Abstract: A memory device includes a substrate, an oxide insulating layer, a first metal oxide layer, a first gate dielectric layer, a second metal oxide layer, a second gate dielectric layer, a first gate, a source, and a drain. The oxide insulating layer is located above the substrate. The first metal oxide layer is located above the oxide insulating layer. The first gate dielectric layer is located above the first metal oxide layer. The second metal oxide layer is located above the first gate dielectric layer. The second gate dielectric layer is located above the second metal oxide layer. The first gate is located above the second gate dielectric layer. The second metal oxide layer is located between the first gate and the first metal oxide layer. The source and the drain are electrically connected to the first metal oxide layer.