Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound semiconductor layer is formed on a first device region and a second device region of a substrate. A III-V compound barrier layer is formed on the III-V compound semiconductor layer. A lamination structure is formed on the III-V compound barrier layer. The lamination structure includes a p-type doped III-V compound layer and a first mask layer disposed thereon. A patterning process is performed to the lamination structure. A first portion of the lamination structure located above the first device region is patterned by the patterning process. A second portion of the lamination structure located above the second device region is removed by the patterning process. A thickness of the second portion of the lamination structure is greater than a thickness of the first portion of the lamination structure before the patterning process.

Abstract: The present invention provides a method and a system for processing session data in an interactive process, a server group, and a computer readable storage medium. A memory module and a protocol configuration module are configured in a gateway server, keywords can be directly extracted by the protocol configuration module from a session of a client and a feedback session of an interactive logic server, and then the keywords can be directly forwarded, so that the throughput of session data processing is improved. The corresponding data is stored, extracted and forwarded by using the memory module, so that the delay of data transmission is reduced. Because the memory module is arranged in the gateway server, the occurrence rate of interface instability can be reduced.

Abstract: A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Abstract: One or more computer processors determine a runtime feature set for a first container, wherein the runtime feature set includes aggregated temporally collocated container behavior. The one or more computer processors cluster the first container with one or more peer containers or peer pods based on a shared container purpose, similar container behaviors, and similar container file structure. The one or more computer processors determine an additional runtime feature set for each peer container. The one or more computer processors calculate a variance between the first container and each peer container. The one or more computer processors, responsive to the calculated variance exceeding a variance threshold, identify the first container as anomalous.

Abstract: A clock synthesizer is provided. The Clock synthesizer includes a a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Abstract: An MOF film comprising an MOF and an organic scaffold. The MOF is attached to the organic scaffold by hydrogen bonds. The MOF film may be a PCMOF and/or HKUST and may have proton conductive properties. The MOF film may comprise a coordinated metal. The organic scaffold may comprise cellulose material. The MOF film may be free standing without physical support from another material or structure, may be formed into shapes, and may be bent or folded. The MOF film may comprise an MOF and an organic scaffold at different weight ratios.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: The present disclosure provides a SARS-CoV-2 vaccine composition and use thereof. The SARS-CoV-2 vaccine composition includes a mutant SARS-CoV-2 spike protein with N-linked glycosylation in N-terminal domain or receptor binding domain, and can effectively elicit an immune response in an individual against different SARS-CoV-2 variants.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: Context information of a handshake between a source entity and a target entity is obtained at a security proxy. The context information is transmitted from the security proxy to a key manager. The key manager maintains a first private key of the security proxy. A first handshake message is received from the key manager. The first handshake message is generated at least based on the context information and signed with the first private key. The first handshake message is then transmitted to the target entity.

Abstract: The present disclosure provides a method for preparing lithium iron phosphate from ferric hydroxyphosphate, including: purifying ferrous sulfate to form a ferrous sulfate solution, adding hydrogen peroxide, phosphoric acid, an ammonium dihydrogen phosphate solution and ammonia water into the ferrous sulfate solution and then reacting to form a mixed slurry, holding the mixed slurry at a temperature for a period of time, and then washing with water and subjecting to press filtration to form ferric hydroxyphosphate precursors with different iron-phosphorus ratios; then flash drying, sintering at a high temperature, and pulverizing to obtain ferric hydroxyphosphate precursors with different iron-phosphorus ratios and different specific surface areas.

Abstract: A method, a computer program product, and a system for implementing a dynamic virtual database honeypot. The method includes relaying a query request received from a database client to a database and receiving, from the database, a response relating to the query request. The method also includes determining the query request is an attack on the database based on session information relating to the database and the database client, generating a honey token based on information contained within the response, generating an alternate response formatted in a same format as the response and containing artificial information that masks the information contained within the response. The method further includes inserting the honey token into the alternate response and transmitting the alternate response to the database client.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.

Abstract: A semiconductor structure includes a substrate including a p-type region and an n-type region, wherein the n-type region is in the p-type region and a distance between a top surface of the substrate and the n-type region is less than a distance between the top surface of the substrate and the p-type region. A buffer layer is over the n-type region and a first III-V compound layer is over the buffer layer. A second III-V compound layer is over the first III-V compound layer and a metal structure is over the second III-V compound layer. The metal structure may include a coplanar waveguide or a high electron mobility transistor.

Abstract: Embodiments described herein relate to a system, methods, and non-transitory computer-readable mediums that accurately align subsequent patterned layers in a photoresist utilizing a deep learning model and utilizing device patterns to replace alignment marks in lithography processes. The deep learning model is trained to recognize unique device patterns called alignment patterns in the FOV of the camera. Cameras in the lithography system capture images of the alignment patterns. The deep learning model finds the alignment patterns in the field of view of the cameras. An ideal image generated from a design file is matched with the camera with respect to the center of the field of view of the camera. A shift model and a rotation model are output from the deep learning model to create an alignment model. The alignment model is applied to the currently printing layer.

Abstract: An example operation may include one or more of receiving a set of structured query language (SQL) queries from one or more software applications, generating a set of SQL syntax trees that correspond to the set of SQL queries, identifying a unique subset of SQL syntax trees among the generated set of SQL syntax trees based on previously obtained SQL syntax trees, and transmitting the unique subset of SQL syntax trees to a computing system.

Abstract: A clock synthesizer is provided. The Clock synthesizer includes a a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.