Abstract: One or more computer processors determine a runtime feature set for a first container, wherein the runtime feature set includes aggregated temporally collocated container behavior. The one or more computer processors cluster the first container with one or more peer containers or peer pods based on a shared container purpose, similar container behaviors, and similar container file structure. The one or more computer processors determine an additional runtime feature set for each peer container. The one or more computer processors calculate a variance between the first container and each peer container. The one or more computer processors, responsive to the calculated variance exceeding a variance threshold, identify the first container as anomalous.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer stores the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit receives the clock signal from the clock buffer, adjusts a duty cycle of the clock signal to substantially equal to 50%, performs phase interpolation on the clock signal, and provides the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: The present disclosure belongs to technical field of cathode materials of lithium batteries, and discloses a preparation method of high-safety high-capacity lithium manganese iron phosphate.

Abstract: The present invention provides a SARS-CoV-2 chimeric VLP vaccine composition and an expressing vector and use thereof. The chimeric SARS-CoV-2 VLP comprises a VLP skeleton formed by the M1 protein and the M2 protein of influenza virus, and the chimeric spike protein of SARS-CoV-2, expressed on the surface of the VLP skeleton, the transmembrane domain of which is replaced by the transmembrane domain of a HA of influenza virus. The present invention also provides a recombinant vector expressing the chimeric SARS-CoV-2 VLP, and the use of the chimeric SARS-CoV-2 VLP for eliciting an immune response against SARS-CoV-2 variants.

Abstract: A database protection system (DPS) mitigates injection attacks. DPS receives an unrestricted database query, extract a syntax tree, and evaluates whether it recognizes the query. To this end, DPS applies a hash function over the extracted syntax tree, and then determines whether the resulting hash has been seen by DPS before. If so, DPS retrieves a previously-generated prepared statement associated with the syntax tree, and that prepared statement is then forward to the database server in lieu of sending the original query. If the syntax tree is not recognized, DPS creates a new prepared statement, generates a hash of the syntax tree, and stores the hash and the new prepared statement, and forwards the new prepared statement. The prepared statements are configured based on the native wire protocol used by the database server, and DPS includes additional functionality by which it can learn the semantics of this protocol if necessary.

Abstract: A method, a computer program product, and a system for implementing a dynamic virtual database honeypot. The method includes relaying a query request received from a database client to a database and receiving, from the database, a response relating to the query request. The method also includes determining the query request is an attack on the database based on session information relating to the database and the database client, generating a honey token based on information contained within the response, generating an alternate response formatted in a same format as the response and containing artificial information that masks the information contained within the response. The method further includes inserting the honey token into the alternate response and transmitting the alternate response to the database client.

Abstract: A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer stores the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit receives the clock signal from the clock buffer, adjusts a duty cycle of the clock signal to substantially equal to 50%, performs phase interpolation on the clock signal, and provides the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: A database protection system (DPS) mitigates injection attacks. DPS receives an unrestricted database query, extract a syntax tree, and evaluates whether it recognizes the query. To this end, DPS applies a hash function over the extracted syntax tree, and then determines whether the resulting hash has been seen by DPS before. If so, DPS retrieves a previously-generated prepared statement associated with the syntax tree, and that prepared statement is then forward to the database server in lieu of sending the original query. If the syntax tree is not recognized, DPS creates a new prepared statement, generates a hash of the syntax tree, and stores the hash and the new prepared statement, and forwards the new prepared statement. The prepared statements are configured based on the native wire protocol used by the database server, and DPS includes additional functionality by which it can learn the semantics of this protocol if necessary.

Abstract: An example operation may include one or more of receiving a set of structured query language (SQL) queries from one or more software applications, generating a set of SQL syntax trees that correspond to the set of SQL queries, identifying a unique subset of SQL syntax trees among the generated set of SQL syntax trees based on previously obtained SQL syntax trees, and transmitting the unique subset of SQL syntax trees to a computing system.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: Context information of a handshake between a source entity and a target entity is obtained at a security proxy. The context information is transmitted from the security proxy to a key manager. The key manager maintains a first private key of the security proxy. A first handshake message is received from the key manager. The first handshake message is generated at least based on the context information and signed with the first private key. The first handshake message is then transmitted to the target entity.

Abstract: A first embodiment is directed to a circuit including a positive biasing circuit with a drive PMOS for biasing in subthreshold, a negative biasing circuit with a drive NMOS for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. The amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. A second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive MOS in subthreshold. A third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive PMOS and a drive NMOS.

Abstract: An example operation may include one or more of receiving a set of structured query language (SQL) queries from one or more software applications, generating a set of SQL syntax trees that correspond to the set of SQL queries, identifying a unique subset of SQL syntax trees among the generated set of SQL syntax trees based on previously obtained SQL syntax trees, and transmitting the unique subset of SQL syntax trees to a computing system.

Abstract: Compounds of Formula (I), racemates, enantiomers, diastereomers thereof or pharmaceutical acceptable salts thereof, or pharmaceutical compositions containing the compounds, racemates, enantiomers, diastereomers thereof, and a manufacturing method thereof are disclosed. These compounds have GPR40 agonist activity and are capable of modulating blood glucose levels and glucose-dependent insulin secretion mechanism, and, thus, exhibit excellent glucose lowering efficacy without the risk of hypoglycemia. These compounds could be used in preventing and/or treating type 2 diabetes through adequate control of blood glucose.

Abstract: A source code analysis tool is augmented to support rule-based analysis of code to attempt to identify certain lexical information indicative of hard-coded secret (e.g., password) support in the code. The tool takes the source code as input, parses the content with a lexical analyzer based on language grammar, and processes the resulting data through preferably a pair of rule-based engines. Preferably, one engine is configured to identify variables explicitly intended to be used as a hard-coded secret, and the other engine is configured to identify data strings that could potentially support such a secret. The outputs of these rules engines are consolidated and evaluated to identify a likelihood that the code under examination includes support for a hard-coded secret. The result is then provided to the developer for further action to address any potential security vulnerability identified by the analysis.