Patents by Inventor Shuo-Nan Hung
Shuo-Nan Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8830754Abstract: A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase.Type: GrantFiled: August 6, 2013Date of Patent: September 9, 2014Assignee: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Shuo-Nan Hung, Chun-Hsiung Hung
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Patent number: 8787078Abstract: Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.Type: GrantFiled: December 13, 2013Date of Patent: July 22, 2014Assignee: Macronix International Co., Ltd.Inventors: Chun Hsiung Hung, Shuo-Nan Hung, Tseng-Yi Liu
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Publication number: 20140198576Abstract: A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set.Type: ApplicationFiled: March 14, 2013Publication date: July 17, 2014Applicant: MACRONIX INTERNATIONAL CO, LTD.Inventors: Shuo-Nan Hung, HANG-TING LUE, TI-WEN CHEN, SHIH-LIN HUANG, KUO-PIN CHANG, CHIH-CHANG HSIEH, CHUN-HSIUNG HUNG
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Patent number: 8760928Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.Type: GrantFiled: December 11, 2012Date of Patent: June 24, 2014Assignee: Macronix International Co. Ltd.Inventors: Ti-Wen Chen, Hang-Ting Lue, Shuo-Nan Hung, Shih-Lin Huang, Chih-Chang Hsieh, Kuo-Pin Chang
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Publication number: 20140160849Abstract: Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled.Type: ApplicationFiled: February 10, 2014Publication date: June 12, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shuo-Nan Hung, Ti Wen Chen
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Patent number: 8738844Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.Type: GrantFiled: April 14, 2011Date of Patent: May 27, 2014Assignee: Macronix International Co., Ltd.Inventors: Lung-Yi Kuo, Hsin-Yi Ho, Chun-Hsiung Hung, Shuo-Nan Hung, Han-Sung Chen
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Patent number: 8724390Abstract: Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.Type: GrantFiled: September 26, 2011Date of Patent: May 13, 2014Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Shuo-Nan Hung, Ji-Yu Hung, Shih-Lin Huang, Fu-Tsang Wang
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Publication number: 20140098616Abstract: Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.Type: ApplicationFiled: December 13, 2013Publication date: April 10, 2014Applicant: Macronix International Co., Ltd.Inventors: Chun Hsiung Hung, Shuo-Nan Hung, Tseng-Yi Liu
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Patent number: 8665646Abstract: Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled.Type: GrantFiled: November 4, 2011Date of Patent: March 4, 2014Assignee: Macronix International Co., Ltd.Inventors: Shuo-Nan Hung, Ti Wen Chen
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Publication number: 20140056072Abstract: A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.Type: ApplicationFiled: October 29, 2013Publication date: February 27, 2014Applicant: Macronix International Co., Ltd.Inventor: Shuo-Nan Hung
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Patent number: 8638618Abstract: An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.Type: GrantFiled: July 19, 2011Date of Patent: January 28, 2014Assignee: Macronix International Co., Ltd.Inventors: Shuo-Nan Hung, Chang Ting Chen, Chi-Yu Hung, Tseng-Yi Liu
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Patent number: 8625343Abstract: Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.Type: GrantFiled: September 9, 2010Date of Patent: January 7, 2014Assignee: Macronix International Co., Ltd.Inventors: Chung-Hsiung Hung, Shuo-Nan Hung, Tseng-Yi Liu
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Publication number: 20130343130Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.Type: ApplicationFiled: December 11, 2012Publication date: December 26, 2013Inventors: TI-WEN CHEN, HANG-TING LUE, SHUO-NAN HUNG, SHIH-LIN HUANG, CHIH-CHANG HSIEH, KUO-PIN CHANG
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Publication number: 20130314997Abstract: A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase.Type: ApplicationFiled: August 6, 2013Publication date: November 28, 2013Applicant: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Shuo-Nan Hung, Chun-Hsiung Hung
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Patent number: 8587998Abstract: A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.Type: GrantFiled: January 6, 2012Date of Patent: November 19, 2013Assignee: Macronix International Co., Ltd.Inventor: Shuo-Nan Hung
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Patent number: 8542532Abstract: A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively provided on a selected stream and on a selected cell of the selected stream, and the rest of memory cells are turned on as pass transistors, in the setup phase. A discharge path is provided to eliminate coupling charge presented on unselected streams, in the setup phase. Then, the string select signal is enabled to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase.Type: GrantFiled: November 17, 2011Date of Patent: September 24, 2013Assignee: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Shuo-Nan Hung, Chun-Hsiung Hung
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Patent number: 8527839Abstract: An on-the-fly repair method for a memory includes: performing a block erase operation on the memory; checking whether the block erase operation is passed or not; finding whether there is any available and healthy redundancy block in the memory if the block erase operation is not passed; programming an address of a failed block to be repaired, an enable bit and at least one error correction bit into both first and second redundancy information regions in a redundancy information set of the memory; checking whether error in the first and the second redundancy information regions is recoverable based on the error correction bit; and if the error is recoverable, then programming the redundancy information set as effective to replace the failed block by the redundancy block related to the effective redundancy information set.Type: GrantFiled: January 31, 2011Date of Patent: September 3, 2013Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Shuo-Nan Hung, Tseng-Yi Liu
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Patent number: 8526235Abstract: Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.Type: GrantFiled: February 27, 2012Date of Patent: September 3, 2013Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Shuo-Nan Hung, Tseng-Yi Liu
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Publication number: 20130208548Abstract: A page copy operation such as copy back programming is performed between a source page of the memory array and a destination page of the memory array in different segments. The segments divide the columns of the main array and the set of redundant columns of the redundant array into, for example, sets of rows. The copy back programming transfers data from a part of the source page in the redundant array to a part of the destination page in the main array, and transfers data from a part of the source page in the main array to a part of the destination page in the redundant array.Type: ApplicationFiled: February 13, 2012Publication date: August 15, 2013Applicant: Macronix International Co., Ltd.Inventor: Shuo-Nan Hung
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Publication number: 20130176781Abstract: A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.Type: ApplicationFiled: January 6, 2012Publication date: July 11, 2013Applicant: Macronix International Co., Ltd.Inventor: Shuo-Nan Hung