Abstract: One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material.

Abstract: One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material.

Abstract: Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases.

Abstract: One method disclosed herein includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming first and second layers of semiconductor material in the fin trench, after forming the second layer of semiconductor material, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, wherein, after the anneal process is performed, the upper surface of the second layer of semiconductor material is substantially defect-free, forming a layer of channel semiconductor material on the upper surface of the second layer of semiconductor material and forming a gate structure around at least a portion of the channel semiconductor material.

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a germanium-based semiconductor substrate including a GeOx layer formed thereon having a first thickness, removing a portion of the GeOx layer by exposing the semiconductor substrate to a NF3/NH3 plasma dry etch so as to reduce the first thickness of the GeOx layer to a second thickness, and depositing a high-k material over the GeOx layer of the semiconductor substrate.

Abstract: One method disclosed herein includes forming a patterned mask layer above a surface of a semiconductor substrate, performing at least one etching process through the patterned mask layer to define a plurality of intersecting ridges that define a ridged surface in the substrate, and forming a Group III-V material on the ridged surface of the substrate. An illustrative device disclosed herein includes a Group IV substrate having a ridged surface comprised of a plurality of intersecting ridges and a Group III-V material layer positioned on the ridged surface of the Group IV substrate.

Abstract: Improvements in a PECVD chamber to provide better uniformity in film thickness and mechanical strength are described. Less contact surface is provided to the outer edge of the wafer and non-uniform gas distribution occurs through adjustments to the gas distribution plate to provide this uniformity.