Abstract: An electrical fuse circuit including: a capacitor composing an electrical fuse; a write circuit breaking an insulating film of the capacitor by applying voltage to between both terminals of the capacitor in accordance with a write signal; and a precharge circuit precharging with respect to the terminal of the capacitor, is provided.

Abstract: An electric fuse circuit is provided which has a capacitor that forms an electric fuse; a write circuit for breaking an insulating film of the capacitor, by applying a voltage to a terminal of the capacitor in response to a write signal; and at least two transistors, including a first transistor and a second transistor, which are connected in series between the capacitor and the write circuit.

Abstract: There is provided a boom assembly bent at the center in a longitudinal direction so as to form a round shape protruding upward when seen from the side, comprising; a front boom sub assembly (47), the front boom sub assembly constituting the front of the center in the longitudinal direction of said boom assembly; and a rear boom sub assembly (48), the rear boom sub assembly constituting the rear of the center in the longitudinal direction of the boom assembly, wherein the front boom sub assembly (47) and the rear boom sub assembly (48) are symmetric when seen from the side, and portions from the midway positions in the longitudinal direction of the front boom sub assembly (47) and the rear boom sub assembly (48) to the center in the longitudinal direction of the boom assembly (12) have upper surfaces of arc shape protruding upward when seen from the side, and portions from the middles in the longitudinal direction of the front boom sub assembly (47) and the rear boom sub assembly (48) to ends in the longitudin

Abstract: A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority. The arbiter disables reception of the internal fresh request in response to a fact that both a chip enable signal and the address valid signal reach a valid level (an external access request). The arbiter enables the reception of the internal refresh request in response to completion of read or write operation. As a result, in a semiconductor memory device including the multipurpose terminal which receives the address signal and the data signal, contention between the read operation and the write operation, and a refresh operation which responds to the internal refresh request is prevented, which prevents a malfunction.

Abstract: A loader control device for controlling a loader implement attached to a tractor is disposed in a position adjacent a driver's seat and does not obstruct the driver boarding or alighting from the tractor. For this purpose, the tractor includes a vehicle body; a loader implement detachably attached to a front part of the vehicle body; a driver's seat mounted on the vehicle body; a steering device disposed forwardly of the driver's seat; a step laid between the driver's seat and the steering device; rear wheel fenders at opposite lateral positions of the driver's seat; and a shifting unit disposed between the driver's seat and one of the rear wheel fenders; wherein a mounting unit for mounting a loader control device for controlling the loader implement is provided in a forward position of an upper surface of the one of the rear wheel fenders.

Abstract: The invention provides a loader work machine with improved front visibility and improved aesthetic appearance. The loader work machine includes a self-propelled machine body, a work device having a boom, a boom cylinder, and a side frame for vertically pivotally supporting base portions of the boom and the boom cylinder, and a frame unit for attaching the work device to the self-propelled machine body. The frame unit has a support platform projecting laterally outward from the self-propelled machine body and a main frame mounted erect on the support platform for supporting and connecting a lower portion of the side frame. An accumulator is connected to the boom cylinder for absorbing shock occurring during a vertical pivotal movement of the work device and this accumulator is attached to the frame unit.

Abstract: A loader work machine including a vehicle body, and a working implement having booms and boom cylinders and mounting frame units for attaching the working implement to a front portion of the vehicle body. Each of the mounting frame units includes a mounting plate fixed to the vehicle body, a support base projecting laterally outward from the mounting plate, a main frame erected on the support base, and a side frame for pivotally supporting proximal ends of one of the booms and one of the boom cylinders. The side frame includes right and left side plates and a connecting element for interconnecting the right and left side plates. The side frame is detachably attached to the main frame by engaging an engaging member disposed in a lower portion of the side frame with an engageable member of the main frame, and connecting a connecting member formed on the side frame to a connectable member formed on the main frame. The main frame is formed as a one-piece plate insertable between the right and left side plates.

Abstract: A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask signal is inputted thereafter is provided.

Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Abstract: A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

Abstract: A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

Abstract: A semiconductor memory device and information processing unit that improve speed at which data is written in a semiconductor memory device. A transfer section transfers data in a burst mode. A transferred number setting section sets the number of a plurality of bits of data transferred in the burst mode. A write command input section receives an input write command. A timing section measures time which has elapsed after the write command being input. A write start time setting section sets time which elapses before the writing of data being begun, according to the number of bits of data set by the transferred number setting section.

Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

Abstract: A semiconductor memory device and information processing unit that improve speed at which data is written in a semiconductor memory device. A transfer section transfers data in a burst mode. A transferred number setting section sets the number of a plurality of bits of data transferred in the burst mode. A write command input section receives an input write command. A timing section measures time which has elapsed after the write command being input. A write start time setting section sets time which elapses before the writing of data being begun, according to the number of bits of data set by the transferred number setting section.

Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

Abstract: The present invention provides inside a scheduler a shift register, which performs a shift operation in synch with an external clock, or a clock generated thereby. Then, for example, when controlling latency from the supply of a command until the start of a column operation, at the time the command is supplied, a column access signal is stored in a shift register location, which corresponds to its latency. Because the shift register performs a shift operation in synch with a clock, a column access signal is outputted subsequent to a number of clock pulses, which correspond to its latency. A column control circuit, in response to the timing at which this column access signal is outputted, acquires a column address and other data required for a column circuitry operation, and starts a column circuitry operation. A configuration such as this simplifies the operation of the scheduler.

Abstract: A latch circuit includes N data latch circuits to which N-bit parallel data are respectively applied where N is an integer, a data input control circuit setting the data latch circuits to a data input state in order, and a data output control circuit which controls the N data latch circuits to output, at different timings, latched data to M output terminals in the order of latch in the N data latch circuits where N.gtoreq.M.gtoreq.1.

Abstract: A semiconductor memory device uses a wave pipeline system which can reduce a power consumption by reducing a current for charging a data bus between a memory core part and an output circuit. A single line data bus transmits read data output from the memory core part. A data bus drive circuit outputs the read read data to send to the single data bus. Each of a plurality of data latch circuits has a data input terminal connected to the data bus. A data input control circuit inputs the read data which is serially transmitted on the data bus to the data latch circuits in parallel in response to an operation of the data bus drive circuit. A data output control circuit outputs the latched read data in an order of latching by sequentially selecting outputs of the data latch circuits.

Abstract: A semiconductor or memory device has a decoder circuit for decoding a plurality of external address signals. The external address signals include first and second external address signals. A first address buffer receives the first external address signals and outputs first internal address signals to first address lines. A second address buffer receives the second external address signals and outputs second internal address signals to second address lines. First predecoders have input terminals connected to the first address lines, and output first predecode signals to first predecode lines. Second predecoders have input terminals connected to the second address lines and output second predecode signals to second predecode lines. Main decoders have input terminals connected to the first predecode lines and the second predecode lines and output decode signals. The number of the first external address signals are greater than the number of the second external address signals.