Patents by Inventor Shusaku Yamaguchi

Shusaku Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5874853
    Abstract: A semiconductor integrated circuit system includes a first power line which supplies a first source power voltage, and a second power line which supplies a second source power voltage. A first edge detecting unit outputs a first edge detection signal when a rising edge of the first source power voltage is detected. A second edge detecting unit outputs a second edge detection signal when a rising edge of the second source power voltage is detected. An output unit is connected to the first power line, and outputs data to a data terminal in a data output cycle and sets the data terminal in a high-impedance state in response to the first edge detection signal. An output control unit is connected to the second power line, and controls the output unit in accordance with a read-data signal in the data output cycle, and controls the output unit in response to the second edge detection signal, so that the data terminal is set in the high-impedance state by the output unit.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: February 23, 1999
    Assignee: Fujitsu Limited
    Inventors: Shusaku Yamaguchi, Atsushi Hatakeyama, Masato Takita, Tadao Aikawa, Hirohiko Mochizuki
  • Patent number: 5841717
    Abstract: A semiconductor memory device includes gates which open in a data-write operation and a data-read operation to allow a passage of data therethrough, and a control circuit changing an open period of the gates between the data-write operation and the data-read operation.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: November 24, 1998
    Assignee: Fujitsu Limited
    Inventor: Shusaku Yamaguchi
  • Patent number: 5828613
    Abstract: There are provided a sense amplifier driving circuit 900 applying a potential VCC/2 to wirings PSA and NSA when a block selecting signal BS0 is at a "L", and applying a potential VCC to the wiring PSA via a pMOS transistor 91 and applying a grounding potential to the wiring NSA via an nMOS transistor 94 when the block selecting signal BS0 is at a "H", and a LDB reset circuit 901A connected between the wiring PSA and a local data bus line pair LDB0 and *LDB0 and including pMOS transistors 95A and 96A which are closed/opened in correspondence to the open/closed state of a column gate 700.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: October 27, 1998
    Assignee: Fujitsu Limited
    Inventors: Atsushi Hatakeyama, Shusaku Yamaguchi