Patents by Inventor Shutesh Krishnan
Shutesh Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942369Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: July 30, 2020Date of Patent: March 26, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wei Wang, Ch Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20240072009Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.Type: ApplicationFiled: October 19, 2023Publication date: February 29, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Vemmond Jeng Hung NG, Shutesh KRISHNAN
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Publication number: 20240030208Abstract: A package includes a dielectric fill material layer embedding a first semiconductor die, a connector clip, and a second semiconductor die. The connector clip has a segment disposed above the dielectric fill material layer embedding the first semiconductor die. This segment of the connector clip is aligned along a same direction as a top surface of the first semiconductor die. The second semiconductor die is disposed on the segment of the connector clip disposed above the dielectric fill material layer.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Chee Hiong CHEW
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Publication number: 20240006266Abstract: A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.Type: ApplicationFiled: September 19, 2023Publication date: January 4, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Mercado TOLENTINO, Shutesh KRISHNAN, Francis J. CARNEY
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Patent number: 11830856Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.Type: GrantFiled: January 17, 2020Date of Patent: November 28, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong Chew, Erik Nino Tolentino, Vemmond Jeng Hung Ng, Shutesh Krishnan
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Patent number: 11776870Abstract: A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.Type: GrantFiled: January 16, 2020Date of Patent: October 3, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Mercado Tolentino, Shutesh Krishnan, Francis J. Carney
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Patent number: 11721654Abstract: A method includes attaching semiconductor die to a carrier between copper pillars, covering with molding, backside grinding to expose first ends of the pillars and backside drain contacts of the die, and applying a layer of conductive material to electrically connect the first ends of the pillars and the backside drain contacts. The method further includes cutting grooves in the conductive material to isolate adjacent die, removing the carrier to expose second ends of the copper pillars in place in the molding, applying another layer of conductive material to electrically connect the second ends of the copper pillars and source contacts of adjacent die, singulating individual MCM packages each including a first die and a second die with a source of the first die connected to a drain of the second die via one of the copper pillars left in place in the molding.Type: GrantFiled: February 22, 2021Date of Patent: August 8, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Nurul Nadiah Manap, Shutesh Krishnan, Soon Wei Wang
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Publication number: 20230246364Abstract: A system for attaching a terminal pin to a circuit trace on an electronic substrate. The system includes a sonotrode and a stage for holding the electronic substrate. The sonotrode is configured to direct ultrasound energy to a base region of the terminal pin placed on the circuit trace to weld the base region to the circuit trace. The system further includes a three-dimensional positioner coupled to the sonotrode. The three-dimensional positioner is configured to drive the sonotrode to lift the terminal pin from a rack and to place the terminal pin on the electronic substrate.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Mercado TOLENTINO, Dennis Cadiz YBORDE, Shutesh KRISHNAN, Pui Leng LOW
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Patent number: 11626677Abstract: A method includes disposing a terminal pin on an electronic substrate with a base region of the terminal pin in contact with a circuit trace on an electronic substrate, and ultrasonically coupling the base region of the terminal pin to the circuit trace.Type: GrantFiled: May 13, 2020Date of Patent: April 11, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Mercado Tolentino, Dennis Cadiz Yborde, Shutesh Krishnan, Pui Leng Low
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Publication number: 20210359445Abstract: A method includes disposing a terminal pin on an electronic substrate with a base region of the terminal pin in contact with a circuit trace on an electronic substrate, and ultrasonically coupling the base region of the terminal pin to the circuit trace.Type: ApplicationFiled: May 13, 2020Publication date: November 18, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Mercado TOLENTINO, Dennis Cadiz YBORDE, Shutesh KRISHNAN, Pui Leng LOW
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Publication number: 20210225730Abstract: A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.Type: ApplicationFiled: January 16, 2020Publication date: July 22, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Mercado TOLENTINO, Shutesh KRISHNAN, Francis J. CARNEY
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Publication number: 20210183799Abstract: A method includes attaching semiconductor die to a carrier between copper pillars, covering with molding, backside grinding to expose first ends of the pillars and backside drain contacts of the die, and applying a layer of conductive material to electrically connect the first ends of the pillars and the backside drain contacts. The method further includes cutting grooves in the conductive material to isolate adjacent die, removing the carrier to expose second ends of the copper pillars in place in the molding, applying another layer of conductive material to electrically connect the second ends of the copper pillars and source contacts of adjacent die, singulating individual MCM packages each including a first die and a second die with a source of the first die connected to a drain of the second die via one of the copper pillars left in place in the molding.Type: ApplicationFiled: February 22, 2021Publication date: June 17, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Nurul Nadiah MANAP, Shutesh KRISHNAN, Soon Wei WANG
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Patent number: 10930604Abstract: A multi-chip module (MCM) includes a molded body portion having a first outer surface and a second outer surface. A conductive layer defines at least a portion of the first outer surface A conductive connection layer portion is disposed outside of the second outer surface of the molded body portion. A first semiconductor die and a second semiconductor die are disposed between the conductive layer and the conductive connection layer, and first molding portion is disposed between the first semiconductor die and the second semiconductor die. The first molding portion extends between the first outer surface and the second outer surface of the molded body portion. A conductive pillar is electrically coupled to the conductive layer defining at least a portion of the first outer surface and the conductive connection layer portion disposed outside of the second outer surface.Type: GrantFiled: March 29, 2018Date of Patent: February 23, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Nurul Nadiah Manap, Shutesh Krishnan, Soon Wei Wang
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Publication number: 20200357697Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw Wei WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
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Publication number: 20200286865Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.Type: ApplicationFiled: January 17, 2020Publication date: September 10, 2020Inventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Vemmond Jeng Hung NG, Shutesh KRISHNAN
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Patent number: 10763173Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: April 26, 2019Date of Patent: September 1, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wei Wang, Ch Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20190304940Abstract: A multi-chip module (MCM) includes a molded body portion having a first outer surface and a second outer surface. A conductive layer defines at least a portion of the first outer surface A conductive connection layer portion is disposed outside of the second outer surface of the molded body portion. A first semiconductor die and a second semiconductor die are disposed between the conductive layer and the conductive connection layer, and first molding portion is disposed between the first semiconductor die and the second semiconductor die. The first molding portion extends between the first outer surface and the second outer surface of the molded body portion. A conductive pillar is electrically coupled to the conductive layer defining at least a portion of the first outer surface and the conductive connection layer portion disposed outside of the second outer surface.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Nurul Nadiah MANAP, Shutesh KRISHNAN, Soon Wei WANG
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Publication number: 20190252255Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw Wei WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
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Patent number: 10319639Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: August 17, 2017Date of Patent: June 11, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wang, CH Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20190057900Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN