Patents by Inventor Shutesh Krishnan

Shutesh Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210359445
    Abstract: A method includes disposing a terminal pin on an electronic substrate with a base region of the terminal pin in contact with a circuit trace on an electronic substrate, and ultrasonically coupling the base region of the terminal pin to the circuit trace.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 18, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Mercado TOLENTINO, Dennis Cadiz YBORDE, Shutesh KRISHNAN, Pui Leng LOW
  • Publication number: 20210225730
    Abstract: A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Mercado TOLENTINO, Shutesh KRISHNAN, Francis J. CARNEY
  • Publication number: 20210183799
    Abstract: A method includes attaching semiconductor die to a carrier between copper pillars, covering with molding, backside grinding to expose first ends of the pillars and backside drain contacts of the die, and applying a layer of conductive material to electrically connect the first ends of the pillars and the backside drain contacts. The method further includes cutting grooves in the conductive material to isolate adjacent die, removing the carrier to expose second ends of the copper pillars in place in the molding, applying another layer of conductive material to electrically connect the second ends of the copper pillars and source contacts of adjacent die, singulating individual MCM packages each including a first die and a second die with a source of the first die connected to a drain of the second die via one of the copper pillars left in place in the molding.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 17, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Nurul Nadiah MANAP, Shutesh KRISHNAN, Soon Wei WANG
  • Patent number: 10930604
    Abstract: A multi-chip module (MCM) includes a molded body portion having a first outer surface and a second outer surface. A conductive layer defines at least a portion of the first outer surface A conductive connection layer portion is disposed outside of the second outer surface of the molded body portion. A first semiconductor die and a second semiconductor die are disposed between the conductive layer and the conductive connection layer, and first molding portion is disposed between the first semiconductor die and the second semiconductor die. The first molding portion extends between the first outer surface and the second outer surface of the molded body portion. A conductive pillar is electrically coupled to the conductive layer defining at least a portion of the first outer surface and the conductive connection layer portion disposed outside of the second outer surface.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 23, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Nurul Nadiah Manap, Shutesh Krishnan, Soon Wei Wang
  • Publication number: 20200357697
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh KRISHNAN, Sw Wei WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
  • Publication number: 20200286865
    Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.
    Type: Application
    Filed: January 17, 2020
    Publication date: September 10, 2020
    Inventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Vemmond Jeng Hung NG, Shutesh KRISHNAN
  • Patent number: 10763173
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: September 1, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Sw Wei Wang, Ch Chew, How Kiat Liew, Fui Fui Tan
  • Publication number: 20190304940
    Abstract: A multi-chip module (MCM) includes a molded body portion having a first outer surface and a second outer surface. A conductive layer defines at least a portion of the first outer surface A conductive connection layer portion is disposed outside of the second outer surface of the molded body portion. A first semiconductor die and a second semiconductor die are disposed between the conductive layer and the conductive connection layer, and first molding portion is disposed between the first semiconductor die and the second semiconductor die. The first molding portion extends between the first outer surface and the second outer surface of the molded body portion. A conductive pillar is electrically coupled to the conductive layer defining at least a portion of the first outer surface and the conductive connection layer portion disposed outside of the second outer surface.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Nurul Nadiah MANAP, Shutesh KRISHNAN, Soon Wei WANG
  • Publication number: 20190252255
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh KRISHNAN, Sw Wei WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
  • Patent number: 10319639
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: June 11, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Sw Wang, CH Chew, How Kiat Liew, Fui Fui Tan
  • Publication number: 20190057900
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 21, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh KRISHNAN, Sw WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
  • Patent number: 10106419
    Abstract: A method of dispersing graphene and graphitic nanomaterials uses a multiphase fluid dynamic technique. The method includes a device, incorporating a high intensity fluid dynamics technique, controlling the expansion and compression ratio of the working stream that leads to an effective dispersion of the nanomaterial in the matrix. The condensation of the injected steam creates high intensity and controllable cavitation, leading to effective dispersion of the graphitic nanomaterial. The dispersion is most preferably done in a medium that creates a repulsive potential to balance the attractive inter-graphitic layer potential.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 23, 2018
    Assignee: GRAPHENE NANOCHEM PLC
    Inventor: Shutesh Krishnan
  • Patent number: 9997485
    Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.
    Type: Grant
    Filed: July 30, 2017
    Date of Patent: June 12, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Yun Sung Won
  • Publication number: 20170352635
    Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.
    Type: Application
    Filed: July 30, 2017
    Publication date: December 7, 2017
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Yun Sung Won
  • Patent number: 9780059
    Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: October 3, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Yun Sung Won
  • Publication number: 20160039679
    Abstract: A method of dispersing graphene and graphitic nanomaterials uses multiphase fluid dynamic technique. The method includes a device, incorporating high intensity fluid dynamics technique (10), controlling the expansion and compression ratio of the working stream that leads to an effective dispersion of the nanomaterial in the matrix. The condensation of the injected steam creates high intensity and controllable cavitation, leading to effective dispersion of the graphitic nanomaterial. The dispersion is most preferably done in a medium that creates a repulsive potential to balance the attractive inter-graphitic layer potential.
    Type: Application
    Filed: July 15, 2015
    Publication date: February 11, 2016
    Inventor: Shutesh Krishnan
  • Publication number: 20140335660
    Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.
    Type: Application
    Filed: July 24, 2014
    Publication date: November 13, 2014
    Inventors: Shutesh Krishnan, Yun Sung Won
  • Patent number: 8519521
    Abstract: An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Chee Hiong Chew, Jatinder Kumar
  • Patent number: 8451621
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes stacked semiconductor die. In accordance with embodiments, the semiconductor component includes a substrate having a component receiving area and a plurality of bond pads. A semiconductor chip is attached to the component receiving area. An electrical connector is coupled to the semiconductor chip and the substrate. A second semiconductor chip is mounted or attached to one of the ends of the electrical connector such that this end is positioned between the semiconductor chips. A second electrical connector is coupled between the second semiconductor chip and the substrate. A third semiconductor chip is mounted over or attached to the second electrical connector such that a portion is between the second and third semiconductor chips.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Soon Wei Wang
  • Patent number: 8449339
    Abstract: A connector assembly and a method for manufacturing the connector assembly. In accordance with embodiments, the connector assembly includes an electrical connector having first and second surfaces and first and second ends. A layer of electrically insulating material is formed from or on a portion of the first surface at the first end. Optionally, a layer of electrically insulating material can be formed from or on the second surface.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Soon Wei Wang