Patents by Inventor Shutesh Krishnan

Shutesh Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10106419
    Abstract: A method of dispersing graphene and graphitic nanomaterials uses a multiphase fluid dynamic technique. The method includes a device, incorporating a high intensity fluid dynamics technique, controlling the expansion and compression ratio of the working stream that leads to an effective dispersion of the nanomaterial in the matrix. The condensation of the injected steam creates high intensity and controllable cavitation, leading to effective dispersion of the graphitic nanomaterial. The dispersion is most preferably done in a medium that creates a repulsive potential to balance the attractive inter-graphitic layer potential.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 23, 2018
    Assignee: GRAPHENE NANOCHEM PLC
    Inventor: Shutesh Krishnan
  • Patent number: 9997485
    Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.
    Type: Grant
    Filed: July 30, 2017
    Date of Patent: June 12, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Yun Sung Won
  • Publication number: 20170352635
    Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.
    Type: Application
    Filed: July 30, 2017
    Publication date: December 7, 2017
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Yun Sung Won
  • Patent number: 9780059
    Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: October 3, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Yun Sung Won
  • Publication number: 20160039679
    Abstract: A method of dispersing graphene and graphitic nanomaterials uses multiphase fluid dynamic technique. The method includes a device, incorporating high intensity fluid dynamics technique (10), controlling the expansion and compression ratio of the working stream that leads to an effective dispersion of the nanomaterial in the matrix. The condensation of the injected steam creates high intensity and controllable cavitation, leading to effective dispersion of the graphitic nanomaterial. The dispersion is most preferably done in a medium that creates a repulsive potential to balance the attractive inter-graphitic layer potential.
    Type: Application
    Filed: July 15, 2015
    Publication date: February 11, 2016
    Inventor: Shutesh Krishnan
  • Publication number: 20140335660
    Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.
    Type: Application
    Filed: July 24, 2014
    Publication date: November 13, 2014
    Inventors: Shutesh Krishnan, Yun Sung Won
  • Patent number: 8519521
    Abstract: An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Chee Hiong Chew, Jatinder Kumar
  • Patent number: 8451621
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes stacked semiconductor die. In accordance with embodiments, the semiconductor component includes a substrate having a component receiving area and a plurality of bond pads. A semiconductor chip is attached to the component receiving area. An electrical connector is coupled to the semiconductor chip and the substrate. A second semiconductor chip is mounted or attached to one of the ends of the electrical connector such that this end is positioned between the semiconductor chips. A second electrical connector is coupled between the second semiconductor chip and the substrate. A third semiconductor chip is mounted over or attached to the second electrical connector such that a portion is between the second and third semiconductor chips.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Soon Wei Wang
  • Patent number: 8449339
    Abstract: A connector assembly and a method for manufacturing the connector assembly. In accordance with embodiments, the connector assembly includes an electrical connector having first and second surfaces and first and second ends. A layer of electrically insulating material is formed from or on a portion of the first surface at the first end. Optionally, a layer of electrically insulating material can be formed from or on the second surface.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Soon Wei Wang
  • Publication number: 20120306066
    Abstract: An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate.
    Type: Application
    Filed: August 20, 2012
    Publication date: December 6, 2012
    Inventors: Shutesh Krishnan, Chee Hiong Chew, Jatinder Kumar
  • Patent number: 8268676
    Abstract: An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: September 18, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Chee Hiong Chew, Jatinder Kumar
  • Publication number: 20120063107
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes stacked semiconductor die. In accordance with embodiments, the semiconductor component includes a substrate having a component receiving area and a plurality of bond pads. A semiconductor chip is attached to the component receiving area. An electrical connector is coupled to the semiconductor chip and the substrate. A second semiconductor chip is mounted or attached to one of the ends of the electrical connector such that this end is positioned between the semiconductor chips. A second electrical connector is coupled between the second semiconductor chip and the substrate. A third semiconductor chip is mounted over or attached to the second electrical connector such that a portion is between the second and third semiconductor chips.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 15, 2012
    Inventors: Shutesh Krishnan, Soon Wei Wang
  • Publication number: 20120064781
    Abstract: A connector assembly and a method for manufacturing the connector assembly. In accordance with embodiments, the connector assembly includes an electrical connector having first and second surfaces and first and second ends. A layer of electrically insulating material is formed from or on a portion of the first surface at the first end. Optionally, a layer of electrically insulating material can be formed from or on the second surface.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 15, 2012
    Inventors: Shutesh Krishnan, Soon Wei Wang
  • Publication number: 20120018864
    Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.
    Type: Application
    Filed: October 11, 2010
    Publication date: January 26, 2012
    Inventors: Shutesh Krishnan, Yun Sung Won
  • Publication number: 20110115061
    Abstract: An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate.
    Type: Application
    Filed: January 29, 2010
    Publication date: May 19, 2011
    Inventors: Shutesh Krishnan, Chee Hiong Chew, Jatinder Kumar
  • Patent number: 7939380
    Abstract: A method for manufacturing a semiconductor component that includes a leadframe having a non-metallic base structure and an intermediate leadframe structure. The non-metallic base structure may be, among other things, paper, cellulose, or plastic. A layer of electrically conductive material is formed over the non-metallic base structure. A circuit element attach structure and a plurality of leadframe leads are formed from the layer of electrically conductive material. A circuit element is coupled to the circuit element attach structure and electrically coupled to the plurality of leadframe leads. The circuit element is encapsulated and at least the non-metallic base structure is removed. Alternatively, a plurality of leadframe leads may be formed on the electrically conductive layer and a circuit element is placed over the electrically conductive layer. The circuit element is electrically coupled to the plurality of leadframe leads and encapsulated.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: May 10, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Soon Wei Wang, Jatinder Kumar
  • Publication number: 20090102028
    Abstract: A method for manufacturing a semiconductor component that includes a leadframe having a non-metallic base structure and an intermediate leadframe structure. The non-metallic base structure may be, among other things, paper, cellulose, or plastic. A layer of electrically conductive material is formed over the non-metallic base structure. A circuit element attach structure and a plurality of leadframe leads are formed from the layer of electrically conductive material. A circuit element is coupled to the circuit element attach structure and electrically coupled to the plurality of leadframe leads. The circuit element is encapsulated and at least the non-metallic base structure is removed. Alternatively, a plurality of leadframe leads may be formed on the electrically conductive layer and a circuit element is placed over the electrically conductive layer. The circuit element is electrically coupled to the plurality of leadframe leads and encapsulated.
    Type: Application
    Filed: March 17, 2008
    Publication date: April 23, 2009
    Inventors: Shutesh Krishnan, Soon Wei Wang, Jatinder Kumar
  • Patent number: 7402895
    Abstract: In one embodiment, a semiconductor package includes a conductive slug and columnar leads in spaced relationship thereto. The columnar leads are coupled to an electronic device attached to the slug, and are exposed at least on one side of the package opposite the die attach slug. The die attach slug is further exposed to provide a package configured in a slug up orientation.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: July 22, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Shutesh Krishnan, Jatinder Kumar
  • Publication number: 20070138610
    Abstract: In one embodiment, a semiconductor package includes a conductive slug and columnar leads in spaced relationship thereto. The columnar leads are coupled to an electronic device attached to the slug, and are exposed at least on one side of the package opposite the die attach slug. The die attach slug is further exposed to provide a package configured in a slug up orientation.
    Type: Application
    Filed: April 14, 2006
    Publication date: June 21, 2007
    Inventors: Shutesh Krishnan, Jatinder Kumar