Patents by Inventor Shuzo Hiraide
Shuzo Hiraide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11736092Abstract: In a phase adjustment circuit, a binary circuit is configured to output a binary signal on the basis of an edge of a video signal. A phase-delayed clock signal generation circuit is configured to generate a phase-delayed clock signal having a later phase than a phase of a clock signal by a first delay amount. A delay time control circuit is configured to cause a phase of the binary signal and the phase of the phase-delayed clock signal to match each other by adjusting the first delay amount. A sampling signal generation circuit is configured to generate a sampling signal having a later phase than the phase of the clock signal by a second delay amount. The second delay amount is in accordance with both a phase shift amount, which is based on the clock signal, and the first delay amount.Type: GrantFiled: August 23, 2022Date of Patent: August 22, 2023Assignee: OLYMPUS CORPORATIONInventors: Takanori Tanaka, Shuzo Hiraide
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Publication number: 20220407501Abstract: In a phase adjustment circuit, a binary circuit is configured to output a binary signal on the basis of an edge of a video signal. A phase-delayed clock signal generation circuit is configured to generate a phase-delayed clock signal having a later phase than a phase of a clock signal by a first delay amount. A delay time control circuit is configured to cause a phase of the binary signal and the phase of the phase-delayed clock signal to match each other by adjusting the first delay amount. A sampling signal generation circuit is configured to generate a sampling signal having a later phase than the phase of the clock signal by a second delay amount. The second delay amount is in accordance with both a phase shift amount, which is based on the clock signal, and the first delay amount.Type: ApplicationFiled: August 23, 2022Publication date: December 22, 2022Applicants: OLYMPUS CORPORATION, OLYMPUS CORPORATIONInventors: Takanori Tanaka, Shuzo Hiraide
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Patent number: 10812099Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.Type: GrantFiled: August 21, 2018Date of Patent: October 20, 2020Assignee: OLYMPUS CORPORATIONInventors: Hideki Kato, Yasunari Harada, Shuzo Hiraide, Masato Osawa
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Patent number: 10757357Abstract: An imaging element includes: a plurality of pixels where each pixel is configured to generate an imaging signal; a noise eliminating circuit configured to eliminate a noise component included in the imaging signal; a plurality of column source follower buffers where each column source follower buffer is configured to amplify the imaging signal from which the noise component has been eliminated by the noise eliminating circuit, and output the amplified signal; a horizontal scanning circuit configured to sequentially select the column source follower buffer and output the imaging signal; and a buffer circuit which is connected with the column source follower buffer sequentially selected by the horizontal scanning circuit to form a voltage follower circuit, the buffer circuit being configured to perform impedance conversion on a voltage of the imaging signal output from the column source follower buffer, and output the converted signal to an outside.Type: GrantFiled: June 17, 2019Date of Patent: August 25, 2020Assignee: OLYMPUS CORPORATIONInventors: Yasunari Harada, Shuzo Hiraide, Masato Osawa, Satoru Adachi
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Patent number: 10700697Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.Type: GrantFiled: August 17, 2018Date of Patent: June 30, 2020Assignee: OLYMPUS CORPORATIONInventors: Masato Osawa, Yasunari Harada, Shuzo Hiraide, Hideki Kato
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Patent number: 10601436Abstract: A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.Type: GrantFiled: May 17, 2019Date of Patent: March 24, 2020Assignee: OLYMPUS CORPORATIONInventors: Shuzo Hiraide, Yasunari Harada, Masato Osawa
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Patent number: 10516410Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.Type: GrantFiled: August 10, 2018Date of Patent: December 24, 2019Assignee: OLYMPUS CORPORATIONInventors: Shuzo Hiraide, Yasunari Harada, Masato Osawa, Hideki Kato
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Publication number: 20190373197Abstract: An imaging element includes: a plurality of pixels where each pixel is configured to generate an imaging signal; a noise eliminating circuit configured to eliminate a noise component included in the imaging signal; a plurality of column source follower buffers where each column source follower buffer is configured to amplify the imaging signal from which the noise component has been eliminated by the noise eliminating circuit, and output the amplified signal; a horizontal scanning circuit configured to sequentially select the column source follower buffer and output the imaging signal; and a buffer circuit which is connected with the column source follower buffer sequentially selected by the horizontal scanning circuit to form a voltage follower circuit, the buffer circuit being configured to perform impedance conversion on a voltage of the imaging signal output from the column source follower buffer, and output the converted signal to an outside.Type: ApplicationFiled: June 17, 2019Publication date: December 5, 2019Applicant: OLYMPUS CORPORATIONInventors: Yasunari HARADA, Shuzo HIRAIDE, Masato OSAWA, Satoru ADACHI
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Publication number: 20190280707Abstract: A disclosed analog-to-digital converter includes; a sampling circuit to sample a pair of analog signals as a differential input signal; a binary capacitance holding the sampled pair of analog signals and reflecting a level of a reference signal to the analog signals through the binary capacitance to generate a pair of voltage signals; a comparator including a transistor to which the voltage signals are input, to compare one of the voltage signals with the other; a correction circuit provided previously to the comparator, to output to the comparator the pair of voltage signals in which voltage dependency of stray capacitance in the input transistor is cancelled; and a controller that successively determines a value of each bit of a digital signal corresponding to the binary capacitance based on a comparison by the comparison circuit, and reflects the value of each bit of the digital signal to the reference signal.Type: ApplicationFiled: May 17, 2019Publication date: September 12, 2019Applicant: OLYMPUS CORPORATIONInventors: Shuzo HIRAIDE, Yasunari HARADA, Masato OSAWA
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Patent number: 10277237Abstract: A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal.Type: GrantFiled: July 24, 2018Date of Patent: April 30, 2019Assignee: OLYMPUS CORPORATIONInventors: Yasunari Harada, Shuzo Hiraide, Masato Osawa, Hideki Kato
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Patent number: 10172512Abstract: A capsule endoscope includes a flexible substrate which is integrally formed by disposing an illumination substrate section, a first wiring substrate section, an imaging element substrate, a second wiring substrate section, and a signal-processing substrate section in a row in sequence and an illumination control circuit which includes an illumination control signal output unit and an illumination driving unit, wherein the light-emitting elements are LEDs, wherein the illumination driving unit is disposed on the imaging element substrate section or the illumination substrate section, and wherein the illumination driving unit includes a transistor array which is formed by a plurality of transistors, the plurality of transistors corresponding to each of the light-emitting elements provided in the illumination unit and generating illumination currents in accordance with the illumination control signal.Type: GrantFiled: August 15, 2016Date of Patent: January 8, 2019Assignee: OLYMPUS CORPORATIONInventor: Shuzo Hiraide
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Publication number: 20180367160Abstract: In an AD converter, a first DAC circuit performs a first operation in parallel with a second operation performed by a second DAC circuit, and the first DAC circuit performs the second operation in parallel with the first operation performed by the second DAC circuit. In the first operation, electric charge corresponding to an input signal of the first DAC circuit or an input signal of the second DAC circuit is sampled. In the second operation, an AD conversion is sequentially performed on the basis of the electric charge sampled in the first operation. The first DAC circuit and the second DAC circuit alternately perform the first operation and the second operation.Type: ApplicationFiled: August 17, 2018Publication date: December 20, 2018Applicant: OLYMPUS CORPORATIONInventors: Masato Osawa, Yasunari Harada, Shuzo Hiraide, Hideki Kato
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Publication number: 20180358977Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Applicant: OLYMPUS CORPORATIONInventors: Hideki Kato, Yasunari Harada, Shuzo Hiraide, Masato Osawa
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Publication number: 20180351568Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.Type: ApplicationFiled: August 10, 2018Publication date: December 6, 2018Applicant: OLYMPUS CORPORATIONInventors: Shuzo Hiraide, Yasunari Harada, Masato Osawa, Hideki Kato
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Publication number: 20180331688Abstract: A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal.Type: ApplicationFiled: July 24, 2018Publication date: November 15, 2018Applicant: OLYMPUS CORPORATIONInventors: Yasunari Harada, Shuzo Hiraide, Masato Osawa, Hideki Kato
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Patent number: 10090851Abstract: A sampling circuit in a successive approximation type analog-to-digital (A/D) converting device samples a pair of analog signals constituting a differential input signal. A capacitor circuit reflects a signal level of a reference signal in the pair of analog signals through an attenuation capacitance unit and a binary capacitance unit to generate a pair of voltage signals. A comparison circuit compares the pair of voltage signals. A control circuit determines a value of each bit of a digital signal on the basis of the result of the comparison and reflects the value in the reference signal. The attenuation capacitance unit includes a fixed capacitance unit connected between a signal node at which the sampled analog signals are held and a predetermined potential node and a variable capacitance unit connected between the signal node and the predetermined potential node in parallel with the fixed capacitance unit.Type: GrantFiled: November 16, 2017Date of Patent: October 2, 2018Assignee: OLYMPUS CORPORATIONInventor: Shuzo Hiraide
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Publication number: 20180083646Abstract: A sampling circuit in a successive approximation type analog-to-digital (A/D) converting device samples a pair of analog signals constituting a differential input signal. A capacitor circuit reflects a signal level of a reference signal in the pair of analog signals through an attenuation capacitance unit and a binary capacitance unit to generate a pair of voltage signals. A comparison circuit compares the pair of voltage signals. A control circuit determines a value of each bit of a digital signal on the basis of the result of the comparison and reflects the value in the reference signal. The attenuation capacitance unit includes a fixed capacitance unit connected between a signal node at which the sampled analog signals are held and a predetermined potential node and a variable capacitance unit connected between the signal node and the predetermined potential node in parallel with the fixed capacitance unit.Type: ApplicationFiled: November 16, 2017Publication date: March 22, 2018Applicant: OLYMPUS CORPORATIONInventor: Shuzo Hiraide
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Publication number: 20160345810Abstract: A capsule endoscope includes a flexible substrate which is integrally formed by disposing an illumination substrate section, a first wiring substrate section, an imaging element substrate, a second wiring substrate section, and a signal-processing substrate section in a row in sequence and an illumination control circuit which includes an illumination control signal output unit and an illumination driving unit, wherein the light-emitting elements are LEDs, wherein the illumination driving unit is disposed on the imaging element substrate section or the illumination substrate section, and wherein the illumination driving unit includes a transistor array which is formed by a plurality of transistors, the plurality of transistors corresponding to each of the light-emitting elements provided in the illumination unit and generating illumination currents in accordance with the illumination control signal.Type: ApplicationFiled: August 15, 2016Publication date: December 1, 2016Applicant: OLYMPUS CORPORATIONInventor: Shuzo Hiraide
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Patent number: 8908026Abstract: An imaging method may include a first step in which light from a test specimen is guided to an imaging unit, a second step in which light from the test specimen is guided to an autofocus unit, a third step in which the light guided to an autofocus unit is split, and is guided on a third optical path and a fourth optical path, a fourth step in which a focal point of the imaging unit is adjusted such that an image of the test specimen that is created by the light from the test specimen guided on the first optical path is formed on an imaging surface of the imaging unit, a fifth step in which an image of the test specimen is acquired and image data is created, a sixth step in which spectrum information for the test specimen is detected, and a seventh step in which a color tone of the image data is corrected.Type: GrantFiled: September 21, 2011Date of Patent: December 9, 2014Assignee: Olympus CorporationInventor: Shuzo Hiraide
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Patent number: 8482820Abstract: An image-capturing system includes: a stage that has mounted and fixed thereon a glass slide on which at least one sample is placed and that circulates in an endless-track shape; a line sensor that scans only a part of the sample; an imaging driving mechanism that moves a relative position of the line sensor and the stage in a direction perpendicular to a scanning direction of the line sensor; and an optical system that focuses an image of the sample on the line sensor.Type: GrantFiled: October 13, 2010Date of Patent: July 9, 2013Assignee: Olympus CorporationInventor: Shuzo Hiraide