Abstract: An imaging method may include a first step in which light from a test specimen is guided to an imaging unit, a second step in which light from the test specimen is guided to an autofocus unit, a third step in which the light guided to an autofocus unit is split, and is guided on a third optical path and a fourth optical path, a fourth step in which a focal point of the imaging unit is adjusted such that an image of the test specimen that is created by the light from the test specimen guided on the first optical path is formed on an imaging surface of the imaging unit, a fifth step in which an image of the test specimen is acquired and image data is created, a sixth step in which spectrum information for the test specimen is detected, and a seventh step in which a color tone of the image data is corrected.

Abstract: An image pickup device may include a stage moving a sample, a line sensor that comprises an imaging element including pixels arranged in a line shape, the line sensor scanning and acquiring an image of the sample, a spectrum detection unit that comprises a first light receiving element including a first color filter and a second light receiving element including a second color filter, the first color filter and the second color filter having different spectral transmittance distributions, the first light receiving element and the second light receiving element scanning a first portion of the sample so as to acquire spectrum information of the first portion, an optical system that introduces a light from the sample to the line sensor and the spectrum detection unit, and a correction device that corrects the image, which has been acquired by the line sensor, based on the spectrum information of the first portion.

Abstract: A photoelectric current integrating circuit including: a first operational amplifier with a switch and an integrating capacitor connected in parallel between an input terminal and an output terminal thereof; a photodiode; and a current passing circuit provided between one terminal of the photodiode and the input terminal of the first operational amplifier, for passing a photoelectric current detected at the photodiode while blocking a connection between a parasitic capacitance of the photodiode and the integrating capacitor.

Abstract: An image-capturing system includes: a stage that has mounted and fixed thereon a glass slide on which at least one sample is placed and that circulates in an endless-track shape; a line sensor that scans only a part of the sample; an imaging driving mechanism that moves a relative position of the line sensor and the stage in a direction perpendicular to a scanning direction of the line sensor; and an optical system that focuses an image of the sample on the line sensor.

Abstract: A photoelectric current integrating circuit including: a first operational amplifier with a switch and an integrating capacitor connected in parallel between an input terminal and an output terminal thereof; a photodiode; and a current passing circuit provided between one terminal of the photodiode and the input terminal of the first operational amplifier, for passing a photoelectric current detected at the photodiode while blocking a connection between a parasitic capacitance of the photodiode and the integrating capacitor.

Abstract: A signal processing circuit for optical encoder, including: a plurality of photodiodes for detecting light in different phase; IV conversion circuits for providing outputs by converting photo currents outputted from a current output terminal of each photodiode respectively into voltage signals; differential amplification circuits for amplifying difference between the output voltage signals corresponding to each photodiode; a DC signal detection circuit for detecting DC components of the photo currents; and a suppressing current generation circuit for supplying suppressing currents for suppressing the DC components to the current output terminals of the photodiodes in accordance with a value of the detected DC components.

Abstract: A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layer superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.

Abstract: A thin-film zinc oxide varistor (10) for use in integrated circuits and the like is produced by applying a polyoxyalkylated metal complex, such as a metal alkoxycarboxylate, to a substrate (12, 14, and 16) for the formation of a dried nonohmic layer (18). The method of production includes the steps of providing a substrate and a precursor solution including a polyoxyalkylated zinc complex (P22, P24), coating a portion of the substrate with the precursor solution (P26), drying the coated substrate (P32), and crystallizing the dried thin-film zinc oxide layer (P30). The resultant crystalline zinc oxide varistor layer (18) may be doped with bismuth, yttrium, praseodymium, cobalt, antimony, manganese, silicon, chromium, titanium, potassium, dysprosium, cesium, cerium, and iron to provide a non-ohmic varistor. The varistor layer (10) is annealed at a temperature ranging from about 400 to about 1000.degree. C.

Abstract: A ferroelectric gate transistor has a structure in which n-type source and drain regions are formed on a p-type semiconductor, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a gate electrode is formed thereon. Memory information is erased by applying a voltage V.sub.g to the ferroelectric to cause poling in the first direction. The memory information is written by applying a voltage V.sub.W lower than a coercive voltage of the ferroelectric and having a polarity opposite to that of the voltage V.sub.g to the ferroelectric. The memory information is read out by applying a voltage V.sub.DR lower than the voltage V.sub.W and having a polarity opposite to that of the voltage V.sub.g to the drain to read a drain current I.sub.DS.

Abstract: A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layered superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.