Patents by Inventor Shwang-Ming Jeng
Shwang-Ming Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230253240Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Patent number: 11664268Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: GrantFiled: July 12, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Publication number: 20210375667Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: ApplicationFiled: July 12, 2021Publication date: December 2, 2021Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Patent number: 11069558Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: GrantFiled: December 13, 2019Date of Patent: July 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Publication number: 20200118867Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Patent number: 10510580Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: GrantFiled: August 16, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Patent number: 10312107Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.Type: GrantFiled: September 8, 2011Date of Patent: June 4, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chi Ko, Chia-Cheng Chou, Shing-Chyang Pan, Keng-Chu Lin, Shwang-Ming Jeng
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Publication number: 20190103304Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.Type: ApplicationFiled: August 16, 2018Publication date: April 4, 2019Inventors: Chin-Hsiang Lin, Keng-Chu Lin, Shwang-Ming Jeng, Teng-Chun Tsai, Tsu-Hsiu Perng, Fu-Ting Yen
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Patent number: 10144109Abstract: A polisher includes a wafer carrier, a polishing head, a movement mechanism, and a rotation mechanism. The wafer carrier has a supporting surface. The supporting surface is configured to carry a wafer thereon. The polishing head is present above the wafer carrier. The polishing head has a polishing surface. The polishing surface of the polishing head is smaller than the supporting surface of the wafer carrier. The movement mechanism is configured to move the polishing head relative to the wafer carrier. The rotation mechanism is configured to rotate the polishing head relative to the wafer carrier.Type: GrantFiled: December 30, 2015Date of Patent: December 4, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Teng-Chun Tsai, Shen-Nan Lee, Yung-Cheng Lu, Chia-Chiung Lo, Shwang-Ming Jeng, Yee-Chia Yeo
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Publication number: 20170190017Abstract: A polisher includes a wafer carrier, a polishing head, a movement mechanism, and a rotation mechanism. The wafer carrier has a supporting surface. The supporting surface is configured to carry a wafer thereon. The polishing head is present above the wafer carrier. The polishing head has a polishing surface. The polishing surface of the polishing head is smaller than the supporting surface of the wafer carrier. The movement mechanism is configured to move the polishing head relative to the wafer carrier. The rotation mechanism is configured to rotate the polishing head relative to the wafer carrier.Type: ApplicationFiled: December 30, 2015Publication date: July 6, 2017Inventors: Teng-Chun TSAI, Shen-Nan LEE, Yung-Cheng LU, Chia-Chiung LO, Shwang-Ming JENG, Yee-Chia YEO
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Patent number: 9589856Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.Type: GrantFiled: November 23, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chou, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
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Patent number: 9368452Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.Type: GrantFiled: February 18, 2014Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Soon-Kang Huang, Han-Hsin Kuo, Chi-Ming Yang, Shwang-Ming Jeng, Chin-Hsiang Lin
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Publication number: 20160086865Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.Type: ApplicationFiled: November 23, 2015Publication date: March 24, 2016Inventors: Chia-Cheng Chou, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
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Patent number: 9196551Abstract: A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.Type: GrantFiled: August 26, 2011Date of Patent: November 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chou, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
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Patent number: 9087877Abstract: A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.Type: GrantFiled: October 24, 2006Date of Patent: July 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chi Ko, Ting-Yu Shen, Keng-Chu Lin, Chia-Cheng Chou, Tien-I Bao, Shwang-Ming Jeng, Chen-Hua Yu
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Patent number: 9004914Abstract: An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller.Type: GrantFiled: June 11, 2013Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chi Ko, Chia Cheng Chou, Keng-Chu Lin, Joung-Wei Liou, Shwang-Ming Jeng, Mei-Ling Chen
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Patent number: 8993435Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.Type: GrantFiled: March 15, 2010Date of Patent: March 31, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Chen Wang, Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
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Patent number: 8877083Abstract: A Ultra-Violet (UV) treatment is performed on an exposed surface of a low-k dielectric layer and an exposed surface of a metal line. After the UV treatment, an organo-metallic soak process is performed on the exposed surface of the low-k dielectric layer and the exposed surface of the metal line. The organo-metallic soak process is performed using a process gas including a metal bonded to an organic group.Type: GrantFiled: November 16, 2012Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chou, Mei-Ling Chen, Hui-Chun Yang, Po-Cheng Shih, Joung-Wei Liou, Shwang-Ming Jeng
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Patent number: 8853858Abstract: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.Type: GrantFiled: August 9, 2012Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Joung-Wei Liou, Keng-Chu Lin, Shwang-Ming Jeng
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Publication number: 20140159243Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.Type: ApplicationFiled: February 18, 2014Publication date: June 12, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Soon-Kang Huang, Han-Hsin Kuo, Chi-Ming Yang, Shwang-Ming Jeng, Chin-Hsiang Lin