Patents by Inventor Shyam P. Murarka

Shyam P. Murarka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated semiconductor circuit structure and method for making it
    Patent number: 4276557
    Abstract: The compounds TiSi.sub.2 and TaSi.sub.2 have been found to be suitable substitutes for polysilicon layers in semiconductor integrated circuits. Suitable conducting properties of the compounds are ensured by providing a relatively thin substrate of polysilicon.
    Type: Grant
    Filed: December 29, 1978
    Date of Patent: June 30, 1981
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Hyman J. Levinstein, Shyam P. Murarka, Ashok K. Sinha
  • Method of limiting stacking faults in oxidized silicon wafers
    Patent number: 4149905
    Abstract: Many of the stacking faults which occur after oxidation of silicon wafers are substantially eliminated by the use of an argon-hydrochloric anneal of the wafers just prior to oxidation. This anneal, which is carried out in the same chamber in which oxidation is carried out, removes impurities from the surface of the wafers and thereby limits the sites at which stacking faults form after oxidation.
    Type: Grant
    Filed: December 27, 1977
    Date of Patent: April 17, 1979
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Hyman J. Levinstein, Robert B. Marcus, Shyam P. Murarka, Richard S. Wagner
  • Passivation of metallized semiconductor substrates
    Patent number: 4134125
    Abstract: Disclosed is a method and structure for protecting circuit components from the ambient and in particular for protecting the contact metal from the adverse effects of moisture. A first layer of amorphous silicon is deposited over the circuit including the metal contacts. A second layer which may be silicon nitride or silicon dioxide is then deposited over the amorphous silicon. The amorphous silicon layer reduces cracking in the second layer and prevents cracks in the second layer from propagating to the circuit components.
    Type: Grant
    Filed: July 20, 1977
    Date of Patent: January 9, 1979
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Arthur C. Adams, Cesar D. Capio, Hyman J. Levinstein, Shyam P. Murarka