Patents by Inventor Shyam Sunder

Shyam Sunder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250139628
    Abstract: Embodiments are directed to adjusting values used for processing of database records. According to one embodiment, how certain database records are processed can be evaluated and certain predefined values used in the processing of those certain records can be adjusted. Upon request, and/or upon the occurrence of certain conditions of events, records of the database can be reviewed and values, e.g., predefined charge values associated with certain services indicated in the records, used to process the records can be adjusted. Generally speaking, an optimization engine can review the records, identify records for evaluation, e.g., records having total amounts limited to a predefined maximum and other records that are consistently below a contractual maximum or too low in general, evaluate those records, and possibly adjust the predefined maximum values based on the evaluation.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 1, 2025
    Inventors: Pieter Schouten, Shyam Sunder, Sashank Rajpurohit
  • Publication number: 20250140322
    Abstract: Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.
    Type: Application
    Filed: July 10, 2024
    Publication date: May 1, 2025
    Inventors: Shyam Sunder Raghunathan, Yingda Dong, Akira Goda, Leo Raimondo
  • Publication number: 20250140323
    Abstract: An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.
    Type: Application
    Filed: July 23, 2024
    Publication date: May 1, 2025
    Inventors: Xiangang Luo, Kishore K. Muchherla, Hong Lu, Akira Goda, Shyam Sunder Raghunathan, Peter Feeley, Emilio Camerlenghi, Paolo Tessariol
  • Publication number: 20250139104
    Abstract: Embodiments are directed to adjusting values used for detection of outlier data in database records. According to one embodiment the records can be reviewed and outlier data stored in one or more of the records can be detected. Outlier data can be considered any data that falls above, below, and/or outside of a range from a value that is expected or which is normal for that data. Detecting the outlier data in the predetermined field can be based on a review process performed on the identified records. Results of a review process can either confirm or correct the identification of the records as including outlier data. If corrections are made, one or more records can be removed from the identified one or more records having outlier data in the predetermined filed based on the received results of the review process.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 1, 2025
    Inventors: Pieter Schouten, Shyam Sunder, Sashank Rajpurohit
  • Patent number: 12271163
    Abstract: A system includes one or more memory devices having instructions stored thereon that, when executed by one or more processors, cause the one or more processors to perform operations including receiving building information model (BIM) data associated with a building comprising one or more building assets, identifying one or more BIM objects within the BIM, identifying one or more object relationships between the one or more BIM object, applying a semantic description to each of the one or more BIM objects and the one or more object relationships, and generating a hierarchy structure for the building based on the one of more BIM objects and the one or more object relationships. The one or more BIM objects are associated with the one or more building assets and the hierarchy structure includes the semantic description of each of the one or more BIM objects and the one or more object relationships.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 8, 2025
    Assignee: TYCO FIRE & SECURITY GMBH
    Inventors: Ashok Sridharan, Ankur Thareja, Subrata Bhattacharya, Barnini Chatterjee, Shailesh Mahadeo Tavate, Shyam Sunder, Sachin Ghorpade, Piyush Mahajan, Akash Kumar
  • Patent number: 12271360
    Abstract: Devices and techniques are generally described for key-value store having improved support for indexing and querying. The proposed system can expand query functionality by adding compound indexing. In some implementations, compound index may allow multiple simple key-value store queries (e.g., for multiple event types) to be replaced with a single query. In some implementations, compound index may allow for query filtering otherwise unavailable for the key-value store. The system may return results from the compound query in timestamp order and with appropriate pagination. Indexing may be updated dynamically; for example, manually via a self-service portal and/or automatically in response to frequent query combinations. The expanded query functionality can improve the efficiency and usability of, for example, an event timeline system.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: April 8, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Natalie Thuy-Tien Nguyen, Shyam Sunder Kumar, Pramod Ramchandra Khare, Joseph G Kim
  • Publication number: 20250104781
    Abstract: A memory device includes an array of memory cells associated with multiple wordlines and control logic operatively coupled with the array. The control logic, in performing a read operation, can determine a length of time that a selected wordline, of the multiple wordlines, takes to reach a pass voltage for reading data from a memory cell associated with the selected wordline. The control logic can select a delay time based on whether the length of time is associated with a transient state or a non-transient state. The control logic can read the data from the memory cell associated with the selected wordline after the selected delay time.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Violante Moschiano, Shyam Sunder Raghunathan, Walter Di Francesco
  • Patent number: 12253996
    Abstract: A solution for automated column type annotation maps each column contained in a table to a column annotation class. A pre-processor transforms the table into a numerical tensor representation by outputting a sequence of cell tokens for each cell in the table. A table encoder encodes the sequences of cell tokens and a column annotation label for each column into body cell embeddings. A body pooling component processes the body cell embeddings to provide column representations. A classifier classifies the column representations to provide for each column, confidence scores for each column annotation class. The method concludes with comparing the highest confidence score for each column with a threshold, and, if the highest confidence score for each column is above the threshold, annotating each column with the respective column annotation class.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: March 18, 2025
    Assignee: Siemens Aktiengesellschaft
    Inventors: Martin Ringsquandl, Mitchell Joblin, Aneta Koleva, Swathi Shyam Sunder
  • Publication number: 20250087275
    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. A first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block: apply a voltage having a first value to a sense line coupled to the plurality of strings; apply a voltage having a second value less than the first value to the first group of access lines; and apply a voltage having a third value less than the second value to the second group of access lines.
    Type: Application
    Filed: July 10, 2024
    Publication date: March 13, 2025
    Inventors: Shyam Sunder Raghunathan, Yingda Dong, Akira Goda
  • Patent number: 12236232
    Abstract: A method, computer program product, and computer system for upgrading, by a computing device, a plurality of storage appliances in a cluster, wherein the storage appliance cluster may include at least a primary storage appliance and a secondary storage appliance. It may be determined that an upgrade to a plurality of storage appliances in a cluster has completed. Distributed data may be queried for each storage appliance in the cluster based upon, at least in part, determining that the upgrade to the plurality of storage appliances in the cluster has completed. Data stored in a management database in the primary storage appliance and data stored locally in the secondary storage appliance may be combined based upon, at least in part, querying the distributed data for each storage appliance in the cluster.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: February 25, 2025
    Assignee: Dell Products L.P.
    Inventors: Venkatesh Madhipatla, Shobhit Nitinkumar Dutia, Shyam Sunder Singaraju, Rajesh Kumar Gandhi, Peixing Sun
  • Publication number: 20250061126
    Abstract: The teachings of the present disclosure relates to data transformation from source data in RDB format to result data in RDF format. Various embodiments of these teachings make source data from e.g., sensors and/or monitoring devices machine readable by transforming datasets in RDB format to datasets in graph dataset format as RDF datasets are.
    Type: Application
    Filed: December 14, 2022
    Publication date: February 20, 2025
    Applicant: Siemens Aktiengesellschaft
    Inventors: Swathi Shyam Sunder, Tobias Aigner, Janaki Joshi
  • Patent number: 12224016
    Abstract: A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: February 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Karan Banerjee, Shyam Sunder Raghunathan
  • Patent number: 12205653
    Abstract: A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: January 21, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Shyam Sunder Raghunathan, Walter Di Francesco
  • Publication number: 20250006292
    Abstract: A method includes detecting a change in a memory control signal of a memory device including memory blocks, determining based at least on the change in the memory control signal that the memory device is in a stable state, and responsive to determining that the memory device is in the stable state, associating a voltage offset bin with at least one memory block of the memory device.
    Type: Application
    Filed: February 13, 2024
    Publication date: January 2, 2025
    Inventors: Taylor Alu, Nicola Ciocchini, Shyam Sunder Raghunathan, Guang Hu, Walter Di Francesco, Umberto Siciliani, Violante Moschiano, Karan Banerjee
  • Publication number: 20250004789
    Abstract: Control logic in a memory device initiates application of a program pulse on a memory array of a memory device as part of a program operation and determines whether a first request to suspend the program operation was received during the application of the program pulse. Responsive to determining that the first request to suspend the program operation was received during the application of the program pulse, the control logic sets a program suspend indicator to a suspend state. Responsive to completing application of the program pulse, the control logic initiates a program verify operation on the memory array, and responsive to completing the program verify operation, determines that the program suspend indicator is set to the suspend state and suspends the program operation.
    Type: Application
    Filed: June 18, 2024
    Publication date: January 2, 2025
    Inventors: Keng Gee Ng, Mohammed Musaiyab Tarapati, Shyam Sunder Raghunathan
  • Publication number: 20250006275
    Abstract: An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. Control circuitry can be configured to: receive a command corresponding to a sensing operation to be performed on a selected access line of a first group of access lines corresponding to a first erase block; and determine an adjusted sense voltage to be applied to the selected access line in association with performing the sensing operation. The adjusted sense voltage is based on: a quantity of the first group of access lines that are programmed; or a quantity of the second group of access lines that are programmed; or both.
    Type: Application
    Filed: June 20, 2024
    Publication date: January 2, 2025
    Inventors: Shyam Sunder Raghunathan, Akira Goda, Kishore K. Muchherla
  • Publication number: 20250006269
    Abstract: A processing device, operatively coupled with a memory device, receives a request to perform a programming operation on a first set of a block addressable by a first wordline of a first die of the memory device, wherein the first die comprises a plurality of decks of the memory device. The processing device identifies, based on a predefined usage type associated with the first die, a deck of the plurality of decks for performing the programming operation; and performing the programming operation on a second set of cells of the block addressable by the first wordline residing on the identified deck of the first die.
    Type: Application
    Filed: April 26, 2024
    Publication date: January 2, 2025
    Inventors: Yu-Chung Lien, Zhenming Zhou, Shyam Sunder Raghunathan, Tingjun Xie
  • Publication number: 20240428178
    Abstract: The present disclosure provides a system and a method for transferring subscriber identifier attribute of label units (110) on replacement. The system includes one or more label units (110) attached to a corresponding object (106) from one or more objects in transit, a first label unit (110-1) replaced by a second label unit (110-2) when said first label unit (110-1) is damaged, wherein a subscriber identifier attribute of the first label unit (110-1) is transferred to the second label unit (110-2) after said replacement. The system includes a tracking system (102) that receives a second set of signals from the second label unit (110-2), updates a database (210) coupled to the tracking system (102) with the second set of unique identifier attributes of the second label unit (110-2), and tracks the objects (106) by receiving one or more tracking and monitoring data from the second label unit (110-2).
    Type: Application
    Filed: August 25, 2023
    Publication date: December 26, 2024
    Applicant: JIO PLATFORMS LIMITED
    Inventors: Gulprit SINGH, Dhananjaya LANKALAPALLI, Vishal Shashikant PATIL, Shyam Sunder MAHESHWARI
  • Publication number: 20240419714
    Abstract: A system and method for data management is provided. The method includes obtaining a dataset from a data source by a processing unit. The dataset includes a plurality of datapoints, and each of the datapoints belongs to a column among a plurality of columns. Further, an ontology label for at least one column in the dataset is predicted using a machine learning model. The predicted ontology label is associated with an ontology comprising a plurality of ontology labels. Further, a mapping between the dataset and the ontology is generated based on the relation between the predicted ontology label and the column. Furthermore, the datapoints are classified with respect to the ontology labels based on the mapping generated. The classified datasets are outputted on a user interface.
    Type: Application
    Filed: September 26, 2022
    Publication date: December 19, 2024
    Inventors: Swathi Shyam Sunder, Nataliia Rümmele, Tobias Aigner, Yogesh Kamath, Rani Joseph, Yogesh Borkhade, Prithvi Raj Ramakrishnaraja
  • Publication number: 20240379176
    Abstract: Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Violante Moschiano, Shyam Sunder Raghunathan, Haiou Che, Walter di Francesco