Patents by Inventor Shyam Sunder

Shyam Sunder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10359769
    Abstract: Embodiments disclosed herein generally relate to methods, systems, and non-transitory computer readable medium for scheduling a substrate processing sequence in an integrated substrate processing system. A client device assigns a processing sequence to each substrate in a batch of substrates to be processed. The client device assigns a processing chamber to each process in the process sequence for each processing chamber in the integrate substrate processing system. The client device generates a processing model for the batch of substrates. The processing model defines a start time for each substrate in each processing chamber. The client device generates a timetable for the batch of semiconductor substrates based off the processing model. The client device processes the batch of substrates in accordance with the timetable.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 23, 2019
    Assignee: Applied Materials, Inc.
    Inventor: Shyam Sunder Emani
  • Publication number: 20190203861
    Abstract: A connector has five or six abutment surfaces for cable ducts. The cable ducts may have substantially square end faces or rectangular end faces half as large. The connector has a main body made of metal, which exhibits one or two square abutment surfaces or portions thereof, and which exhibits four smaller substantially rectangular abutment surfaces.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 4, 2019
    Inventors: Mario Hinderer, Chandrashekar Radhakrishnan, Shyam Sunder Bhadya, Herbert Velten, Marco Willi
  • Publication number: 20190086906
    Abstract: Embodiments disclosed herein generally relate to methods, systems, and non-transitory computer readable medium for scheduling a substrate processing sequence in an integrated substrate processing system. A client device assigns a processing sequence to each substrate in a batch of substrates to be processed. The client device assigns a processing chamber to each process in the process sequence for each processing chamber in the integrate substrate processing system. The client device generates a processing model for the batch of substrates. The processing model defines a start time for each substrate in each processing chamber. The client device generates a timetable for the batch of semiconductor substrates based off the processing model. The client device processes the batch of substrates in accordance with the timetable.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Inventor: Shyam Sunder EMANI
  • Publication number: 20180253669
    Abstract: This disclosure relates to a method and system for creating a dynamic canonical data model. The method includes creating staging tables to analyze regulatory data collected from a plurality of heterogeneous sources. The method further includes creating a dynamic canonical ontology based on the staging tables representing the regulatory data. The dynamic canonical ontology determines a plurality of attributes associated with the regulatory data and relationships amongst the plurality of attributes. The method includes identifying automatically at least one modification associated with at least one of the plurality of attributes by applying machine learning techniques on the staging tables. The method further includes updating the dynamic canonical ontology by adding the at least one modification to create the dynamic canonical data model.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 6, 2018
    Inventors: Shyam Sunder Thunoli, Rahul Krishna Deshpande, Rohit Sardeshpande, Harshad Subhash Borgaonkar
  • Patent number: 10043574
    Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 7, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Sunder Raghunathan, Pranav Kalavade, Krishna K. Parat, Charan Srinivasan
  • Publication number: 20180218540
    Abstract: A system for locating a target in a building includes a mobile application and a remote system. The mobile application is for implementation on a mobile device including a camera configured to be utilized by the mobile application to selectively obtain a first image data of a first environment. The remote system is configured to selectively receive the first image data from the mobile application. The remote system is also configured to compare, in response to receiving the first image data from the mobile application, the first image data to a database of targets. The remote system is also configured to determine if a portion of the first image data is indicative of a target in the database of targets.
    Type: Application
    Filed: January 16, 2018
    Publication date: August 2, 2018
    Applicant: Johnson Controls Technology Company
    Inventors: Ashok Sridharan, Jeeva S, Jayesh Patil, Subrata Bhattacharya, Shyam Sunder M, Ankur Thareja
  • Publication number: 20180190347
    Abstract: Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shyam Sunder Raghunathan, Pranav Kalavade, Krishna K. Parat, Charan Srinivasan
  • Patent number: 10011591
    Abstract: The present invention provides a crystalline Form I of afatinib dimaleate, its process for preparation and pharmaceutical composition thereof, and its use in the treatment of metastatic non-small cell lung cancer.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: July 3, 2018
    Assignee: Sun Pharmaceutical Industries Limited
    Inventors: Shravan Kumar Singh, Shyam Sunder Verma, Kaptan Singh, Mohan Prasad
  • Publication number: 20180122487
    Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.
    Type: Application
    Filed: September 26, 2017
    Publication date: May 3, 2018
    Inventors: Shantanu R. RAJWADE, Pranav KALAVADE, Neal R. MIELKE, Krishna K. PARAT, Shyam Sunder RAGHUNATHAN
  • Patent number: 9922704
    Abstract: Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: March 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Sunder Raghunathan, Pranav Kalavade, Krishna K. Parat, Charan Srinivasan
  • Patent number: 9793819
    Abstract: Certain embodiments of the present invention relates to a method for controlling operation of a parallel converter system. The parallel converter system includes multiple parallel power converters, and each of the parallel power converters is coupleable to a corresponding controller. The method includes: generating, via each of the controllers, a channel reference signal, transmitting each of the generated channel reference signals to a corresponding one of the parallel power converters, and adjusting an output current of each of the parallel converters responsive to the corresponding channel reference signals received, the adjusting controlling a combined output current of the parallel converter system. The channel reference signals of these parallel power converters are generated in response to the participation factors of each of the parallel power converters, and a net converter output reference current.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 17, 2017
    Assignee: GE ENERGY POWER CONVERSION TECHNOLOGY LTD
    Inventors: Shyam Sunder Ramamurthy, Luke Anthony Solomon, Brian Babes Venus, Christopher Joseph Lee
  • Patent number: 9792997
    Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Shantanu R. Rajwade, Pranav Kalavade, Neal R. Mielke, Krishna K. Parat, Shyam Sunder Raghunathan
  • Patent number: 9788056
    Abstract: Methods and systems for a media guidance application that may stimulate the senses of users. The media guidance application may determine a preferred biometric state associated with a media asset, determine a current biometric measurement of a user, cross-reference the preferred biometric state in a database to determine a difference in sensory stimulation between the current biometric state of the user and the preferred biometric state, and cause the user to be stimulated to account for the difference.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 10, 2017
    Assignee: Rovi Guides, Inc.
    Inventors: Shyam Sunder Vijay, Walter R. Klappert
  • Patent number: 9758471
    Abstract: The present invention provides a process for the preparation of 4-dimethylaminocrotonic acid of Formula (II) or its salts, which is used as an intermediate for the preparation of afatinib or its salts.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: September 12, 2017
    Assignee: Sun Pharmaceutical Industries Limited
    Inventors: Shyam Sunder Verma, Shravan Kumar Singh, Kaptan Singh, Mohan Prasad
  • Publication number: 20170240533
    Abstract: The present invention provides a crystalline Form I of afatinib dimaleate, its process for preparation and pharmaceutical composition thereof, and its use in the treatment of metastatic non-small cell lung cancer.
    Type: Application
    Filed: October 1, 2015
    Publication date: August 24, 2017
    Applicant: Sun Pharmaceutical Industries Limited
    Inventors: Shravan Kumar SINGH, Shyam Sunder VERMA, Kaptan SINGH, Mohan PRASAD
  • Publication number: 20170163165
    Abstract: Certain embodiments of the present invention relates to a method for controlling operation of a parallel converter system. The parallel converter system includes multiple parallel power converters, and each of the parallel power converters is coupleable to a corresponding controller. The method includes: generating, via each of the controllers, a channel reference signal, transmitting each of the generated channel reference signals to a corresponding one of the parallel power converters, and adjusting an output current of each of the parallel converters responsive to the corresponding channel reference signals received, the adjusting controlling a combined output current of the parallel converter system. The channel reference signals of these parallel power converters are generated in response to the participation factors of each of the parallel power converters, and a net converter output reference current.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 8, 2017
    Inventors: Shyam Sunder RAMAMURTHY, Luke Anthony SOLOMON, Brian Babes VENUS, Christopher Joseph LEE
  • Publication number: 20170149350
    Abstract: A method, apparatus, and system to control a multi-phase converter having at least one power channel with a plurality of power modules, and involves detecting the voltage and the current of the power modules, calculating a command voltage based on a product of a programmed virtual resistance and the detected current, and transmitting a command voltage signal to the power modules based on the calculated command voltage.
    Type: Application
    Filed: November 19, 2015
    Publication date: May 25, 2017
    Inventors: Shyam Sunder RAMAMURTHY, Christopher Joseph LEE, Luke Anthony SOLOMON
  • Publication number: 20170107172
    Abstract: The present invention provides a process for the preparation of 4-dimethylaminocrotonic acid of Formula (II) or its salts, which is used as an intermediate for the preparation of afatinib or its salts.
    Type: Application
    Filed: June 2, 2015
    Publication date: April 20, 2017
    Applicant: SUN PHARMACEUTICAL INDUSTRIES LIMITED
    Inventors: Shyam Sunder VERMA, Shravan Kumar SINGH, Kaptan SINGH, Mohan PRASAD
  • Patent number: 9563882
    Abstract: A method and a system perform software suite activation. In some embodiments, a method includes installing a software suite having a number of software products onto a computer device. If a copy of one of the number of software products is already activated on the computer device, the installing includes deactivating a license of the copy of the one of the number of software products. Additionally, if a copy of one of the number of software products is already activated on the computer device, the installing includes adopting, by the software suite, the copy of the one of the number of software products.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: February 7, 2017
    Assignee: Adobe Systems Incorporated
    Inventors: Shyam Sunder Vijay, Xuejun Xu
  • Patent number: 9535777
    Abstract: Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Pranav Kalavade, Feng Zhu, Shyam Sunder Raghunathan, Ravi H. Motwani