Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

Abstract: Electronic devices may include displays having organic light-emitting diode pixels, display driver circuitry, and gate driver circuitry. To reduce the amount of space occupied in the inactive area of a display by the gate driver circuitry, one or more of the shift registers in the gate driver circuitry may include register circuits that are shared by multiple rows of pixels. Different drivers may use different clock frequencies to ensure synchronous operation of the display even when some register circuits share pixel rows. For increased flexibility in the arrangement of the register circuits in the shift registers, one or more of the shift registers may be split across the active area of the display. In some cases, one of the emission drivers may be omitted from the gate driver circuitry and a single emission driver may provide multiple emission control signals for the pixels.

Abstract: Electronic devices may include displays having organic light-emitting diode pixels, display driver circuitry, and gate driver circuitry. To reduce the amount of space occupied in the inactive area of a display by the gate driver circuitry, one or more of the shift registers in the gate driver circuitry may include register circuits that are shared by multiple rows of pixels. Different drivers may use different clock frequencies to ensure synchronous operation of the display even when some register circuits share pixel rows. For increased flexibility in the arrangement of the register circuits in the shift registers, one or more of the shift registers may be split across the active area of the display. In some cases, one of the emission drivers may be omitted from the gate driver circuitry and a single emission driver may provide multiple emission control signals for the pixels.

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: Electronic devices may include displays having organic light-emitting diode pixels, display driver circuitry, and gate driver circuitry. To reduce the amount of space occupied in the inactive area of a display by the gate driver circuitry, one or more of the shift registers in the gate driver circuitry may include register circuits that are shared by multiple rows of pixels. Different drivers may use different clock frequencies to ensure synchronous operation of the display even when some register circuits share pixel rows. For increased flexibility in the arrangement of the register circuits in the shift registers, one or more of the shift registers may be split across the active area of the display. In some cases, one of the emission drivers may be omitted from the gate driver circuitry and a single emission driver may provide multiple emission control signals for the pixels.

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

Abstract: A display may have an array of pixels. Due to the presence of a notch in the display, the display may have some rows that are shorter than other rows in the display, and accordingly different gate line loading. To account for the gate line loading variations, the display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. In other arrangement, luminance adjustment circuitry may receive image data and generate corresponding compensated image data to account for gate line loading variations between rows of pixels in the display. The image data may be compensated based on the location of the pixel, the gray level of the image data, the display brightness, and/or temperature.

Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may include a drive transistor coupled in series with one or more emission transistors and a respective organic light-emitting diode (OLED). A semiconducting-oxide transistor may be coupled between a drain terminal and a gate terminal of the drive transistor to help reduce leakage during low-refresh-rate display operations. A silicon transistor may be further interposed between the semiconducting-oxide transistor and the gate terminal of the drive transistor. One or more capacitor structures may be coupled to the source terminal and/or the drain terminal of the semiconducting-oxide transistor to reduce rebalancing current that might flow through the semiconducting-oxide transistor as it is turned off. Configured in this way, any emission current flowing through the OLED will be insensitive to any potential drift in the threshold voltage of the semiconducting-oxide transistor.

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may include a drive transistor coupled in series with one or more emission transistors and a respective organic light-emitting diode (OLED). A semiconducting-oxide transistor may be coupled between a drain terminal and a gate terminal of the drive transistor to help reduce leakage during low-refresh-rate display operations. A silicon transistor may be further interposed between the semiconducting-oxide transistor and the gate terminal of the drive transistor. One or more capacitor structures may be coupled to the source terminal and/or the drain terminal of the semiconducting-oxide transistor to reduce rebalancing current that might flow through the semiconducting-oxide transistor as it is turned off. Configured in this way, any emission current flowing through the OLED will be insensitive to any potential drift in the threshold voltage of the semiconducting-oxide transistor.

Abstract: Aspects of the subject technology relate to display circuitry. The display circuitry includes gate-in-panel (GIP) control circuitry on opposing sides of a display pixel array. The GIP control circuitry can include scan drivers for each pixel row on both sides of that pixel row, the scan drivers on either side configured for enablement or disablement for single-sided reduced-power operations. The GIP control circuitry can include a single scan driver and a single emission controller for each pixel row, in which the scan driver and emission controller for each row are disposed on opposing sides of the row. The scan drivers for a first subset of the pixel rows can be interleaved with the emission controllers for a different subset of the pixel rows.

Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.

Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.