Abstract: A quadrature phase oscillator in a Radio Frequency (RF) transceiver Integrated Circuit (IC) is provided. The quadrature phase oscillator includes a voltage controlled oscillator and a filter. The voltage controlled oscillator provides an oscillating frequency for modulation of a transmission/reception signal according to an applied voltage. The filter receives the oscillating frequency from the voltage controlled oscillator as an input, passes one of a negative frequency component of the input oscillating frequency and a positive frequency component of the input oscillating frequency, attenuates the other frequency component, generates an I (In phase) signal that is in phase with the input oscillating frequency and a Q (Quadrature phase) signal having a phase difference of 90° with the input oscillating frequency for the passed frequency component, and outputs the I signal and the Q signal.

Abstract: An apparatus and method are provided for controlling power in sleep mode in a mobile communication terminal. A radio communicator including a power supply converts a radio signal received through an antenna into a baseband signal using a reference oscillating frequency of a voltage controlled oscillator. A radio frequency identification (RFID) tag generates power using an interrogation signal from a base station, and outputs a “wake-up” signal to be used to determine whether a radio signal has been received using the generated power. A controller controls the power supply to supply the power to the radio communicator in response to the wake-up signal from the RFID tag. Accordingly, an amount of power consumption in the mobile communication terminal can be reduced.

Abstract: An Ultra Wide Band (UWB) transmitting and receiving device that includes a Digital Signal Processor (DSP) for implementing a DC offset cancellation algorithm, an adder for adding a baseband transmission signal from the transmitter and a calibration signal produced by the algorithm of the DSP, a modulator for modulating the signal from the adder, a transmitter amplifier for amplifying the modulated signal, a coupler for applying the output of the transmitter to the receiver, and a switch for selectively connecting the output of the coupler to the input of the receiver.

Abstract: An ultra wide band (UWB) pulse train generator, which includes a trigger signal controller for sequentially outputting n trigger signals for triggering generation of UWB pulse train in accordance with n bit data to be transmitted at a predetermined time period, a latch unit for loading in parallel the n bit data to be transmitted and sequentially toggling the loaded n bit data by one bit whenever the trigger signal is input from the trigger signal controller, and a pulse train generator for generating polarity pulses corresponding to a direction of an edge transition in accordance with toggling on each output signal of the latch unit.

Abstract: The present invention relates to a precision fullwave rectifier which is used in communication systems or non-linear signal processors. The present invention used in communication systems and non-linear signal processors includes an input part receiving a first alternating current input signal and a second alternating current input between which a phase difference of about 180° exists wherein the input part generates a first current and a fourth current proportional to the first alternating current input signal and also generates a second current and a third current proportional to the second alternating current input signal, a first current subtractor outputting a fifth current by subtracting the second current from the first current, a second current subtractor outputting a sixth current by subtracting the fourth current from the third current, and an output part transforming and generate an wave-rectified output voltage by adding the fifth current to the sixth current.

Abstract: Sensing circuit for a semiconductor device and a sensing method using the same which allows sensing of a selected nonvolatile memory cell at a low voltage, a low power, and a fast speed, and has a high sensing reliability, the circuit including a bitline connected to a drain terminal of a memory cell through a Y-decoder, a senseline for sensing, and forwarding a data in the memory cell, a switching unit for switching between the bitline and the senseline, a first current supply unit disposed between a power source and the bitline for supplying a current to the bitline to the memory cell, a second current supply unit disposed between the power source and the senseline for supplying a current to the senseline, a voltage level shifter for providing a voltage difference between the bitline and the senseline, and a sense MOS transistor disposed between the senseline and the ground voltage and having a gate terminal connected to one end of the voltage level shifter.

Abstract: A device and method for sensing data in a multi-bit memory cell of a memory cell array unit is provided where each memory cell has at least two threshold voltage levels. The device can include a multistep current source unit to provide quantized voltages, each having a width smaller than a threshold voltage distribution in a selected memory cell, according to a current flowing through the selected memory cell. An analog-to-digital converter compares the quantized voltages from the multistep current source unit with a plurality of reference voltages to provide a state of the memory cell in binary form. The device and method for sensing data in the multi-bit memory cell uses the quantized voltages to increase sensing reliability, increases sensing speed and increases a gap between the quantized voltages relative to the threshold voltage distribution.