Abstract: Disclosed is a cover window using a plastic rather than a glass, and a method for manufacturing the same. The cover window, includes: a base material layer formed of a transparent plastic material; a black layer stacked on one surface of the base material layer and formed along a periphery of the base material layer; an elastomer layer formed to surround both the base material layer and the black layer; a fixing member spaced apart at a certain interval from the elastomer layer and formed on the black layer; and a rear surface coating layer stacked on a portion of a surface of the black layer between the elastomer layer and the fixing member.

Abstract: Disclosed is a cover window using a plastic rather than a glass, and a method for manufacturing the same. The cover window includes: a base material layer formed of a transparent plastic material; a black layer stacked on one surface of the base material layer and formed along a periphery of the base material layer; a print layer stacked on another surface of the base material layer; and a coating layer stacked on one surface of the print layer.

Abstract: Disclosed is a cover window using a plastic rather than a glass, and a method for manufacturing the same. The cover window includes: a base material layer formed of a transparent plastic material; a black layer stacked on one surface of the base material layer and formed along a periphery of the base material layer; and an elastomer layer formed to surround another surface of the base material layer and one surface of the black layer.

Abstract: The present invention relates to an organic compound represented by the following Formula 1, and a high-efficiency and long-lifetime organic light emitting device enabling significantly improved low voltage driving, and having long lifetime, excellent luminous efficiency and the like by employing the same as a light emitting layer host material in the device.

Abstract: Disclosed is a cover window using a plastic rather than a glass, and a method for manufacturing the same. The cover window, includes: a base material layer formed of a transparent plastic material; and a black layer stacked on one surface of the base material layer and formed along a periphery of the base material layer. With this configuration, there is an effect of reducing manufacturing costs, preventing a safety accident that may occur due to breakage by using a plastic rather than a glass and preventing deterioration of adhesion and discoloration of the base material layer and the black layer when dual injection is conducted.

Abstract: The present invention relates to an organic compound represented by the following Formula 1, and a high-efficiency and long-lifetime organic light emitting device enabling significantly improved low voltage driving, and having long lifetime, excellent luminous efficiency and the like by employing the same as a light emitting layer host material in the device.

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Abstract: A microelectronic device includes a stack structure with tiers individually extending through an array area and into a staircase area horizontally neighboring the array area. The array area includes at least one access device. The staircase area includes a staircase structure having steps at ends of the tiers. At least some of the tiers individually include a conductive region, insulative regions, and discrete regions of semiconductor material. The conductive region includes conductive material extending through the array area and into the staircase area. The insulative regions are in both the array area and the staircase area. The discrete regions of semiconductor material are in the array area. The staircase area is substantially free of the semiconductor material. The conductive material is thicker in the staircase area than in the array area. Related electronic systems and methods of formation are also disclosed.

Abstract: Provided is an encapsulant film composition; including an ethylene/alpha-olefin copolymer and a crosslinking aid comprises a compound represented by Formula 1 below, an encapsulant film, and a solar cell module thereof. When an encapsulant film is produced using the encapsulant film composition, the immersing time of an ethylene/alpha-olefin copolymer is reduced so that the economic viability of a process of producing an encapsulant film can be improved. In addition, the encapsulant film composition produced exhibits excellent crosslinking degree. wherein R1 to R6 are described herein.

Abstract: The present invention relates to an organic compound represented by the following [Formula 1], and a high-efficiency and long-lifetime organic light emitting device enabling significantly improved low voltage driving and having long lifetime, excellent luminous efficiency and the like by employing the same as a light emitting layer host material in the device.

Abstract: Some implementations herein provide for a memory device and methods of formation. The memory device includes a plurality of storage cells arranged vertically and a plurality of corresponding gate all around transistors. Methods of forming the memory device include using a single trench to remove a liner material and form recesses that define cell contact lightly-doped drain regions of the gate all around transistors. Using the single trench to remove the liner material and form the recesses that define the cell contact lightly-doped drain region widths causes the cell contact lightly-doped drain regions to be formed having substantially similar widths.

Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

Abstract: Methods, systems, and devices for multi-layer capacitors for three-dimensional memory systems are described. Memory cells of a memory system may include capacitors having dielectric material between multiple interfaces (e.g., concentric interfaces) of a bottom electrode and a top electrode. A bottom electrode may include a first portion wrapping around a portion of a semiconductor material that is contiguous with a channel of a transistor, and a top electrode may include a first portion wrapping around the first portion of the bottom electrode. The bottom electrode may also include a second portion wrapping around the first portion of the top electrode, and the top electrode may also include a second portion wrapping around the second portion of the bottom electrode. The dielectric material may include respective portions between each interface of the bottom electrode and top electrode which, in some examples, may be a contiguous implementation of the dielectric material.

Abstract: Methods, systems, and devices for doping of memory cell selection transistors are described. Cell selection transistors of an array of memory cells may each include a semiconductor channel that is doped at a middle portion of the channel, which may support a deselection voltage for relatively high channel resistance that is relatively closer to or equal to a ground voltage than other transistor configurations. The semiconductor channels may include a p-type doping (e.g., using a configured concentration of boron) at a middle portion of the channels that is between end portions that are doped with an n-type doping (e.g., using phosphorous, arsenic, or a combination thereof, among other examples of n-type doping). In some implementations, undoped regions may be included between the n-type doped portions and the p-type doped portions. Such techniques may be implemented in horizontal cell selection transistors formed over a substrate, including for three-dimensional memory arrays.

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a memory device may include a memory array that includes multiple stacks of vertically stacked memory cells. The memory device may include a transistor positioned above a stack of vertically stacked memory cells of the multiple stacks of vertically stacked memory cells. The transistor may include a channel positioned above the stack of vertically stacked memory cells, a first source/drain region on top of a first portion of the channel, a second source/drain region on top of a second portion of the channel, a gate having a top surface that is lower than a top surface of the first source/drain region and that is lower than a top surface of the second source/drain region, and a gate dielectric that separates the gate from the channel.

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Systems, methods and apparatus are provided for two transistor cells for vertical three-dimensional memory. The memory has pairs of serially connected transistors, each pair of serially connected transistors having an independent first source/drain region and a shared second source/drain region separated by channel regions; horizontally oriented access lines separated from the channel regions by a gate dielectric material; and vertically oriented digit lines electrically coupled to the first source/drain regions of the serially connected transistors.

Abstract: Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprising a transistor comprise a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A gate is operatively-proximate the channel region. A capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. The first capacitor electrode is directly electrically coupled to the first source/drain region. The second capacitor electrode of multiple of the capacitors is directly electrically coupled with one another. Digitlines extend elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory-cell tiers are directly electrically coupled to individual of the digitlines.

Abstract: Some embodiments include apparatuses in which one of the apparatuses includes a first conductive structure, a second conductive structure, a third conductive structure, and a memory cell. The memory cell includes a semiconductor portion located on a first level of the apparatus and coupled to the first conductive structure, and a charge storage structure located on the first level coupled to the semiconductor portion and separated from the second conductive structure. The third conductive structure is located on a second level of the apparatus adjacent the semiconductor portion, and including first, second, and third conductive regions. The third conductive region is located between the first and second conductive regions and has a material different from a material of the first conductive region and a material of the second conductive region.