Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

Abstract: Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have epitaxially grow single crystal silicon to fill the first horizontal opening and house a first source/drain in electrical contact with a conductive material and to form part of an integral, horizontally oriented, conductive digit line. The memory cells also have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain region.

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Abstract: Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.

Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric.

Abstract: A microelectronic device comprises semiconductive pillar structures each individually comprising a digit line contact region disposed laterally between two storage node contact regions. At least one semiconductive pillar structure of the semiconductive pillar structures comprises a first end portion comprising a first storage node contact region, a second end portion comprising a second storage node contact region, and a middle portion between the first end portion and the second end portion and comprising a digit line contact region, a longitudinal axis of the first end portion oriented at an angle with respect to a longitudinal axis of the middle portion. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A microelectronic device comprises semiconductive pillar structure comprising a central portion, a first end portion, and a second end portion on a side of the central portion opposite the first end portion, the first end portion oriented at an angle with respect to the central portion and extending substantially parallel to the second end portion, a digit line contact on the central portion of the semiconductive pillar structure, a first storage node contact on the first end portion, and a second storage node contact on the second end portion. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: Systems, methods and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. A plurality of first vertical openings are formed through the vertical stack to form elongated vertical, pillar columns with sidewalls in the vertical stack. A first conductive material is conformally deposited on a gate dielectric material in the first vertical openings. Portions of the first conductive material are removed to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns.

Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region of the sacrificial material. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening.

Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The three-node access devices include a first source/drain region (1) and a second source/drain region (2) separated by a channel and gates (3) opposing the channel, but do not have a direct, electrical body contact to a body region and/or channel of the access devices. The method includes depositing alternating layers of a dielectric material and a sacrificial semiconductor material in repeating iterations to form a vertical stack, a first region of the sacrificial semiconductor material in which to form a first and a second source/drain region separated laterally by a channel region. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent the first region.

Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening.

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

Abstract: Systems, methods and apparatus are provided for forming layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeating iterations vertically to form a vertical stack and forming a vertical opening using an etchant process to expose vertical sidewalls in the vertical stack. A seed material that is selective to the semiconductor material is deposited over the vertical stack and the vertical sidewalls in the vertical stack and the seed material is processed such that the seed material advances within the semiconductor material such that it transforms a crystalline structure of a portion of the semiconductor material.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric.

Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices.

Abstract: Systems, methods, and apparatus are provided for storage node after horizontally oriented, three-node access device formation in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial semiconductor material to form a vertical stack. A first vertical opening is formed through the vertical stack to expose a first region of the sacrificial semiconductor material. The first region is selectively removed to form a first horizontal opening in which to replace a sacrificial gate dielectric material, form a source/drain conductive contact material, a channel conductive material, and a digit line conductive contact material of the three-node access device.

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.