Abstract: A memory controller, system and method for storing data blocks in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from. The method includes generating one or more error checking data blocks based upon the plurality of data blocks; and storing the plurality of data blocks and the error checking data block(s) in the distinct physical non-volatile memory devices, with each data block in a different physical memory device. The method links the addresses of the data blocks and the error checking data block(s) in a cyclical link so that any entry to one of the data blocks will result in a link to all of the other data blocks. The memory controller has a processor and a memory for storing programming code for performing the foregoing method.

Abstract: A system and method for a solid state drive comprising a system controller and one or more extender devices coupled to the system controller is disclosed, where each extender device is coupled to a plurality of NAND storage devices and each NAND storage device comprising a plurality of NAND flash memory cells.

Abstract: A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.

Abstract: An output buffer circuit for a non-volatile memory comprises an error check circuit, an error correction circuit, a switch circuit, and three storage circuits. The error check circuit receives the plurality of data bits and the plurality of ECC bits from the non-volatile memory to determine if the plurality of data bits need to be corrected and generates a correction signal. The error correction circuit receives the plurality of data bits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. A switch enables the output buffer circuit to concurrently performs operations of error check, error correction, and transfer of data bits out of the output buffer circuit on three distinct pluralities of data bits. The switch allows reallocation of storage circuits to different operations without any data transfer.

Abstract: A host device connected to memory devices, with each memory device having NAND memory chips and an associated controller. Each NAND memory chip can store a page of data in a single write operation, and can read a page of data from NAND memory in a single read operation, with the page being the smallest unit of storage and having a plurality of bits. The controller of each memory chip partitions each page of the associated NAND memory chip into first, second and third locations. The first location is for storage of host data. The second location is for storage of controller meta data. The third location is for storage of meta data of the host device associated with the host data. The host data, meta data of the controller, and meta data of the host device are written into or read from a page in a single operation.

Abstract: A method for controlling the storage of a plurality of blocks of sequential data in a plurality of independent NAND memory devices, where each NAND memory device can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The method includes assigning a different NAND memory device to each different block of data received for storage and for storing the plurality of blocks of data in the plurality of different NAND memory devices. Efficiency of readout of sequential blocks of data is improved. The present invention also comprises a memory controller having a processor and a non-volatile memory for storing programming code that can perform the foregoing method. Finally, the present invention is a memory system that has a plurality of NAND memory devices device that can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from.

Abstract: A method of storing a plurality of blocks of data in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from, wherein each block of data is the minimum amount of data that can be written to or read from the non-volatile memory device. The method includes generating one or more blocks of error checking data based upon the plurality of blocks of data; and storing the plurality of blocks of said data and the one or more blocks of error checking data in the plurality of distinct physical non-volatile memory devices, with a block of data in a different physical memory device. Further, the method links the address of the plurality of blocks of data and the one or more blocks of error checking data in a cyclical link so that any entry to one of the blocks will result in a link all of the other blocks.

Abstract: An output buffer circuit for a non-volatile memory stores a plurality of data bits and a plurality of error correction check (“ECC”) bits associated with the plurality of data bits. The output buffer circuit comprises an error check circuit for receiving the plurality of data bits and the plurality of ECC bits to determine if the plurality of data bits need to be corrected. The error check circuit supplies the plurality of data bits as its output, and generates a correction signal. An error correction circuit receives the plurality of data hits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. The output buffer circuit further has three or more storage circuits with each storage circuit having an input/output port.

Abstract: A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.

Abstract: A NAND memory chip has a plurality of blocks with each block having a certain amount of storage and wherein the amount of storage in each block is the minimum amount that is erasable as a group. A controller controls the NAND memory chip. The method of operating the controller comprises writing data into a block of the NAND memory chip to partially fill the block. Then the controller tracks the extent to which the block has been written. After the block is partially written, the step is stopped. The controller determines if a request to the NAND memory chip needs to be serviced. The controller resumes the writing into the block after servicing the request. The present invention also relates to a method for controlling, the operation of a memory device having a controller for interfacing with and controlling a NAND memory. The memory device is responsive to either serial or parallel ATA protocol commands supplied from a host.

Abstract: A USB switching device can selectively connect between a removable card and a mobile wireless communication device and a computer. The removable card has a first port; the mobile wireless communicating device has a second port while the computer has a third port. The switching device comprises a first full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a second full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a third full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output.

Abstract: A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories.

Abstract: A NOR emulating memory device has a memory controller with a first bus for receiving a NOR command signal, and for servicing a read operation from a desired address in a NOR memory. The memory controller has a second bus for communicating with a NAND memory in a NAND memory protocol, and a third bus for communicating with a RAM memory. A NAND memory is connected to the second bus. The NAND memory has an array of memory cells divided into a plurality of pages with each page divided into a plurality of sectors, with each sector having a plurality of bits. The NAND memory further has a page buffer for storing a page of bits read from the array during the read operation of the NAND memory. A RAM memory is connected to the third bus.

Abstract: A non-volatile storage system comprises a hard disk drive (HDD) having a first capacity for storing information therein in a plurality of blocks. The storage system also comprises a non-volatile solid state memory (SSD) having a second capacity, less than the first capacity, for storing information therein. Finally, the storage system comprises a controller having a volatile memory and for controlling the read operation of the HDD and the read/write operation of the SSD. The controller stores in the volatile memory the address of read blocks from the HDD in a first period of time and determines a plurality of the most frequently read blocks in the first period of time, The controller then causes the SSD to store information from the most frequently read blocks from the HDD, and thereafter causes information to be read from the SSD when the storage system is requested to access information from the most frequently read blocks.

Abstract: A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories.

Abstract: In the present invention, a memory, and in particular, a NOR emulating memory comprises a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller. The controller has a first bus for receiving address signals from a host device and a second bus for interfacing with a RAM memory, and a third bus for interfacing with a NAND memory. A volatile RAM memory is connected to the second bus. A NAND memory is connected to the third bus. The controller receives commands and a first address from the first bus, and maps the first address to a second address in the NAND memory, and operates the NAND memory in response thereto. The RAM memory serves as cache for data to or from the NAND memory. The controller also maintains data coherence between the data stored in the RAM memory as cache and the data in the NAND memory.

Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.