Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Abstract: An apparatus and method are described for implementing handling of exceptions caused by speculated instructions in a CPU having speculative execution capabilities. A CPU implementing speculative execution contains a speculative bit register file. Each speculative bit in the speculative bit register file is logically associated with a particular general purpose register, while remaining physically separate. This is accomplished through the use of a physically separate register file (the speculative bit register file) and register selection circuitry allowing simultaneous access to the two register files. The present invention provides instruction execution hardware supporting speculative execution with minimal impact on computational and structural complexity.

Abstract: A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture efficiently executes software code by providing the processor with a grouper circuit which receives software code instructions from a secondary memory and groups these instructions based upon the content of the instructions and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.

Abstract: Apparatus and method for enabling substantially simultaneous access to consecutive entries in an addressable translation memory. The addressable translation memory may be either direct mapped or multi-way set associative. An address decoder receives input address signals and generates output select signals. Each input address signal and each output select signal corresponds to one of the registers in the translation memory. The invention includes a plurality of primary select lines, each of which transmits one of the output select signals to its corresponding register. The invention also includes a plurality of secondary select lines, each of which transmits an output select signal corresponding to a particular register to a second register, the particular register and the second register storing consecutive entries in the translation memory. The particular register and the second register receive the output select signal substantially simultaneously.

Abstract: A vector processor with a vector mask control unit provides an efficient approach for execution of conditional loops by a vector processor. The vector mask control unit includes respective vector masks for source and destination vector registers to specify the vector elements that should participate in the execution operation. Only the vector elements that correspond to active mask elements then participate in the execution operation, thus increasing the efficiency of the vector processor in executing conditional loops. Providing a vector mask control unit also allows the vector processor to perform a variety of functions more efficiently.

Abstract: A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture, efficiently executes old software code by providing the processor with a compatibility circuit which receives old software code instructions from a secondary memory, groups these instructions according the new instruction set architecture and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.

Abstract: A computing system is described in which groups of individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. During compilation of the instructions those which can be executed in parallel are identified. The system includes a register for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags and group identification tags indicative of the pipeline to which they should be dispatched, and the group of instructions which may be dispatched during the same operation. The pipeline and group identification tags are used to dispatch the appropriate groups of instructions simultaneously to the differing pipelines.