Abstract: An internet protocol telephone includes a substrate having an input and an output that are capable of being connected to the internet protocol (IP) network. A relay is disposed on the substrate and is connected between the input and the output of the substrate. The relay includes first and second native FETs that have a threshold voltage of approximately zero volts. Therefore, the relay is nominally turned-on, even when little or no voltage (or power) is applied to the IP telephone substrate, as during the discovery mode of IP telephone operation. During discovery mode, The IP phone is configured to be responsive to extended link pulses and block data packets that are associated with legacy devices. Data packets have a higher signal duration and are more continuous than extended link pulses. The IP phone includes a switchable ground that is connected to the gates of the native devices, and is controlled by a rectifier and filter circuit that are connected to the substrate input.

Abstract: An internet protocol telephone includes a substrate having an input and an output that are capable of being connected to the internet protocol (IP) network. A relay is disposed on the substrate and is connected between the input and the output of the substrate. The relay includes first and second native FETs that have a threshold voltage of approximately zero volts. Therefore, the relay is nominally turned-on, even when little or no voltage (or power) is applied to the IP telephone substrate, as during the discovery mode of IP telephone operation. During discovery mode, The IP phone is configured to be responsive to extended link pulses and block data packets that are associated with legacy devices. Data packets have a higher signal duration and are more continuous than extended link pulses. The IP phone includes a switchable ground that is connected to the gates of the native devices, and is controlled by a rectifier and filter circuit that are connected to the substrate input.

Abstract: An Internet Protocol (IP) telephone has a constant impedance filter that is capable of being continuously attached to the physical layer of a computer chip in the IP telephone. The constant impedance filter is located outside the physical layer and is connected to a relay on the physical layer. The relay is configured using native FET devices, which are normally conductive without a supply voltage. Therefore, the relay is capable of operating during the discovery mode of IP telephone operation, where no power is applied to the substrate. Rectifier circuits rectify an incoming signal during discovery mode, and apply the rectified signal to the gate of the relay to improve conductivity of the relay. This allows for faster detection of the IP telephone during discovery mode. During normal operation mode, voltage is applied to the physical layer, and the relay is opened by grounding the native devices.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: An Internet Protocol (IP) telephone has a constant impedance filter that is capable of being continuously attached to the physical layer of a computer chip in the IP telephone. The constant impedance filter is located outside the physical layer and is connected to a relay on the physical layer. The relay is configured using native FET devices, which are normally conductive without a supply voltage. Therefore, the relay is capable of operating during the discovery mode of IP telephone operation, where no power is applied to the substrate. Rectifier circuits rectify an incoming signal during discovery mode, and apply the rectified signal to the gate of the relay to improve conductivity of the relay. This allows for faster detection of the IP telephone during discovery mode. During normal operation mode, voltage is applied to the physical layer, and the relay is opened by grounding the native devices.

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system. The controlling system includes a controller and one or more state machines that are used to control the TDR system.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: A method and apparatus that minimizes saturation caused by power transfer in a communication system transformer, such as a transformer found in a Power-over-Ethernet system. A magnetic flux imbalance causing saturation in the transformer is detected. A compensation current is injected into a winding to minimize the magnetic flux imbalance and saturation.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system.

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system. The controlling system includes a controller and one or more state machines that are used to control the TDR system.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system. The controlling system includes a controller and one or more state machines that are used to control the TDR system.

Abstract: An internet protocol telephone includes a substrate having an input and an output that are capable of being connected to the internet protocol (IP) network. A relay is disposed on the substrate and is connected between the input and the output of the substrate. The relay includes first and second native FETs that have a threshold voltage of approximately zero volts. Therefore, the relay is nominally turned-on, even when little or no voltage (or power) is applied to the IP telephone substrate, as during the discovery mode of IP telephone operation. During discovery mode, The IP phone is configured to be responsive to extended link pulses and block data packets that are associated with legacy devices. Data packets have a higher signal duration and are more continuous than extended link pulses. The IP phone includes a switchable ground that is connected to the gates of the native devices, and is controlled by a rectifier and filter circuit that are connected to the substrate input.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A programable gain amplifier (PGA) has an amplifier and a variable resistor that is connected to the output of the amplifier. The variable resistor includes a resistor that is connected to a reference voltage and multiple parallel taps that tap off the resistor. A two-stage switch network having fine stage switches and coarse stage switches connects the resistor taps to an output node of the PGA. The taps and corresponding fine stage switches are arranged into two or more groups, where each group has n-number of fine stage switches and corresponding taps. One terminal of each fine stage switch is connected to the corresponding resistor tap, and the other terminal is connected to an output terminal for the corresponding group. The coarse stage switches select from among the groups of fine stage switches, and connect to the output of the PGA.

Abstract: A constant impedance filter maintains a constant input impedance for frequencies that are both inside the filter passband and outside the filter passband. The constant input impedance appears as a pure resistance. The constant impedance filter includes a plurality of filter poles that are connected in series. Each of the filter poles include an inductor, a capacitor, and a resistor. The value of the inductor, the capacitor, and the resistor are selected to provide a constant input impedance over frequency for each pole of the filter, which produces a constant input impedance for the entire filter over frequency. The constant impedance filter can be implemented as a low pass filter, a high pass filter, or a bandpass filter. Furthermore, the constant impedance filter can be implemented in a single-ended configuration or a differential configuration.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.