Patents by Inventor Siddharth Gupta

Siddharth Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12670940
    Abstract: Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.
    Type: Grant
    Filed: September 30, 2024
    Date of Patent: June 30, 2026
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hemavathi Chaya, Nilesh Panchal, H Harish, Siddharth Gupta
  • Publication number: 20260154257
    Abstract: A system, method, and computer-readable medium for proving feedback on database instructions, identifying, for example, existing patterns and providing suggested replacement instructions. This may have the effect of improving the efficiency of instructions used to create and/or manipulate databases. According to some aspects, these and other benefits may be achieved by parsing received instructions into an organizational structure, traversing the organizational structure for known patterns, and suggesting replacement patterns. In implementation, this may be effected by receiving one or more sets of known patterns and corresponding replacement patterns, parsing received instructions, comparing the known patterns with the parsed instructions, and providing suggested replacement patterns based on one or more known patterns matching the parsed instructions. A benefit of may include reducing Cartesian products during the merging of tables.
    Type: Application
    Filed: January 26, 2026
    Publication date: June 4, 2026
    Inventors: Dennis J. Mire, Puneet Goyal, Siddharth Gupta, Srinivas Kumar, Deepak Sundararaj, Oron Hazi
  • Publication number: 20260145317
    Abstract: A robot may include a body, a control system, and a control interface. The control system may be configured to cause the robot to transition between an autonomous mode and an intervention mode. In the autonomous mode, the control system may be configured to autonomously control the body within an environment, In the intervention mode, the control system may be configured to control the body within the environment based on operator input. The control interface may be configured to receive the operator input.
    Type: Application
    Filed: November 24, 2025
    Publication date: May 28, 2026
    Inventors: Brandon Porter, Jon Stevens, Alan Baird, Michael Vogelsong, Siddharth Gupta, Michael Lammers
  • Patent number: 12640737
    Abstract: A circuit includes an input-output, a supply terminal, a reference terminal, a high-side transistor, a low-side transistor, a driver, and a bias generation circuit. The driver circuit includes a first inverter having an output, a second inverter having an input, an output, and first and second supply inputs, and a transmission gate having an input, an output, and first and second enable inputs. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transmission gate is coupled to the output of the driver, the first supply input of the second inverter is coupled to the output of the transmission gate, and the second supply input of the second inverter is coupled to a reference terminal.
    Type: Grant
    Filed: August 28, 2024
    Date of Patent: May 26, 2026
    Assignee: Texas Instruments Incorporated
    Inventors: Siddharth Gupta, Sneha Shetty
  • Publication number: 20260100300
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to resistor trimming structures and methods of use. The structure includes: a set of resistors each of which include an increasing resistance value; and a set of switches each of which are connected to a respective resistor of the set of resistors and each of which comprise a decreasing width dimension for each resistor of increasing resistance value.
    Type: Application
    Filed: October 7, 2024
    Publication date: April 9, 2026
    Inventors: Siddharth Gupta, Sandeep Tripathi, Pruthvi Muchharla Hariprasad, Lejan Pu, Devesh Dwivedi
  • Publication number: 20260094634
    Abstract: Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.
    Type: Application
    Filed: September 30, 2024
    Publication date: April 2, 2026
    Inventors: Hemavathi Chaya, Nilesh Panchal, H Harish, Siddharth Gupta
  • Publication number: 20260095183
    Abstract: A semiconductor device includes a low voltage-to-high voltage level shifter structured to receive a low voltage signal and output a high voltage signal. The level shifter includes a buffer structured to receive the low voltage input signal. The buffer includes a pullup transconductor having a negative transconductance, a pulldown transconductor having a positive transconductance, and a cutoff transconductor having a positive transconductance, coupled in series. The pullup transconductor and the pulldown transconductor are structured to be controlled by the low voltage input signal. The cutoff transconductor is structured to be controlled by a delayed cutoff signal that inversely corresponds to the low voltage input signal. A pullup assist transconductor having a negative transconductance is connected to an output of the buffer. The pullup assist transconductor is structured to be controlled by a delayed reset signal corresponding to the delayed cutoff signal.
    Type: Application
    Filed: October 2, 2024
    Publication date: April 2, 2026
    Inventors: Sneha Shetty, Siddharth Gupta, Sridhar Singhal
  • Publication number: 20260095182
    Abstract: A semiconductor device includes a low voltage-to-high voltage level shifter. The level shifter is structured to receive a low voltage signal and output a high voltage signal. The level shifter includes a buffer structured to receive the low voltage input signal. The buffer includes a pullup transconductor, a pulldown transconductor, and a cutoff transconductor, coupled in series. The pullup transconductor has a negative transconductance and is structured to be controlled by the low voltage input signal. The pulldown transconductor has a positive transconductance and is structured to be controlled by the low voltage input signal The cutoff transconductor has a positive transconductance and is structured to be controlled by a delayed high voltage cutoff signal that inversely corresponds to the low voltage input signal.
    Type: Application
    Filed: September 30, 2024
    Publication date: April 2, 2026
    Inventors: Sneha Shetty, Siddharth Gupta, Sridhar Singhal
  • Publication number: 20260073715
    Abstract: The present disclosure generally relates to systems and techniques for geospatial image processing. Certain aspects of the present disclosure provide a method for geospatial image processing. The method generally includes providing a user interface for annotating one or more geospatial images, receiving at least one annotation for the one or more geospatial images from a user device, generating a training dataset based on the at least one annotation, and training a first machine learning model for features identification in geospatial images via the training dataset.
    Type: Application
    Filed: November 4, 2022
    Publication date: March 12, 2026
    Inventors: SIDDHARTH GUPTA, SAGAR VERMA
  • Publication number: 20260066902
    Abstract: A circuit includes an input-output, a supply terminal, a reference terminal, a high-side transistor, a low-side transistor, a driver, and a bias generation circuit. The driver circuit includes a first inverter having an output, a second inverter having an input, an output, and first and second supply inputs, and a transmission gate having an input, an output, and first and second enable inputs. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transmission gate is coupled to the output of the driver, the first supply input of the second inverter is coupled to the output of the transmission gate, and the second supply input of the second inverter is coupled to a reference terminal.
    Type: Application
    Filed: August 28, 2024
    Publication date: March 5, 2026
    Inventors: Siddharth Gupta, Sneha Shetty
  • Patent number: 12561316
    Abstract: A system, method, and computer-readable medium for proving feedback on database instructions, identifying, for example, existing patterns and providing suggested replacement instructions. This may have the effect of improving the efficiency of instructions used to create and/or manipulate databases. According to some aspects, these and other benefits may be achieved by parsing received instructions into an organizational structure, traversing the organizational structure for known patterns, and suggesting replacement patterns. In implementation, this may be effected by receiving one or more sets of known patterns and corresponding replacement patterns, parsing received instructions, comparing the known patterns with the parsed instructions, and providing suggested replacement patterns based on one or more known patterns matching the parsed instructions. A benefit of may include reducing Cartesian products during the merging of tables.
    Type: Grant
    Filed: June 4, 2024
    Date of Patent: February 24, 2026
    Assignee: Capital One Services, LLC
    Inventors: Dennis J. Mire, Puneet Goyal, Siddharth Gupta, Srinivas Kumar, Deepak Sundararaj, Oron Hazi
  • Publication number: 20260032126
    Abstract: Techniques are described through which groups of individuals and/or other entities may interface with a data cloud blockchain network and/or cloud-based platform to collectively share data in a secure, controlled manner. Decentralized groups that are connected to the data cloud network may be registered and listed in a searchable directory. Entities that are interested in accessing data associated with a group may browse the directory, execute smart contracts within a blockchain, and track online content interactions of a group in a manner that does not compromise the anonymity of individual group members. Data usage and performance metrics may be tracked on the blockchain network using data cloud services, and the metrics may be written to distributed ledgers within the blockchain network. Smart contracts and chaincode within the network may initiate blockchain transactions based on performance metrics and/or other aspects associated with accessing information about a group.
    Type: Application
    Filed: September 26, 2025
    Publication date: January 29, 2026
    Applicant: Oracle International Corporation
    Inventor: Siddharth Gupta
  • Patent number: 12483560
    Abstract: Techniques are described through which groups of individuals and/or other entities may interface with a data cloud blockchain network and/or cloud-based platform to collectively share data in a secure, controlled manner. Decentralized groups that are connected to the data cloud network may be registered and listed in a searchable directory. Entities that are interested in accessing data associated with a group may browse the directory, execute smart contracts within a blockchain, and track online content interactions of a group in a manner that does not compromise the anonymity of individual group members. Data usage and performance metrics may be tracked on the blockchain network using data cloud services, and the metrics may be written to distributed ledgers within the blockchain network. Smart contracts and chaincode within the network may initiate blockchain transactions based on performance metrics and/or other aspects associated with accessing information about a group.
    Type: Grant
    Filed: January 24, 2023
    Date of Patent: November 25, 2025
    Assignee: Oracle International Corporation
    Inventor: Siddharth Gupta
  • Patent number: 12425338
    Abstract: Various embodiments include methods of managing mixed data flow types in communications in a network apparatus. The network apparatus may determine data flow priority levels of a plurality of data flows, identify high-priority data flows associated with a particular LAN interface, and assign a designated public IP address range or a designated public port range for the high-priority data. Upon receiving an uplink, the apparatus may select a source port number from the previously reserved range dedicated for high-priority data flows in response to the received packet matching one or more prioritized data flow packet filters, modify the received uplink packet, and forward the modified uplink packet to the next hop in the path towards the destination IP address in response to determining that the packet is enqueued successfully.
    Type: Grant
    Filed: January 17, 2024
    Date of Patent: September 23, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Feilu Liu, Suli Zhao, Siddharth Gupta, Alok Mitra
  • Patent number: 12419487
    Abstract: A method for operating a water-bearing household appliance for treating articles, in particular a dishwasher or washing machine, the water-bearing household appliance including a treatment chamber for treating the articles with a washing liquor and a dosing system for dispensing a dosing-amount of detergent provided by a dosing unit, the method comprising: selecting one of a plurality of different treatment cycles, controlling the water-bearing household appliance to perform the selected treatment cycle, actuating the dosing system to dispense the dosing-amount of detergent according to the selected treatment cycle, detecting a sensor signal of the dispensed dosing-amount of detergent, adjusting the selected treatment cycle as a function of the detected sensor signal, and controlling the water-bearing household appliance to perform the adjusted treatment cycle.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 23, 2025
    Assignees: Reckitt Benckiser (Brands) Limited, BSH Hausgeräte GmbH
    Inventors: Jakob Schultz, Alexander Schiele, Daniel Köhler, Henry Matthew Lawrence Fletcher, Matthew Burrows, Siddharth Gupta
  • Publication number: 20250291459
    Abstract: Systems and methods described herein relate to contextual navigation for embedded analytics integrations. An embedded analytics user interface is presented within a first application. The embedded analytics user interface is provided by a second application and includes a plurality of user-selectable data items of the second application. A user selection of a first data item from among the plurality of user-selectable data items is detected via the embedded analytics user interface. Context data related to the user selection is identified. The context data is identified based at least partially on a stored mapping between the first data item of the second application and a second data item of the first application. One or more navigation options associated with the context data are obtained from the first application. An interface element that includes the one or more navigation options is presented within the embedded analytics user interface.
    Type: Application
    Filed: March 12, 2024
    Publication date: September 18, 2025
    Inventors: Arpitha A. Shetty, Aneesh Shukla, Siddharth Gupta, Mahesh Sivasubramani, Sanjay S
  • Publication number: 20250233826
    Abstract: Various embodiments include methods of managing mixed data flow types in communications in a network apparatus. The network apparatus may determine data flow priority levels of a plurality of data flows, identify high-priority data flows associated with a particular LAN interface, and assign a designated public IP address range or a designated public port range for the high-priority data. Upon receiving an uplink, the apparatus may select a source port number from the previously reserved range dedicated for high-priority data flows in response to the received packet matching one or more prioritized data flow packet filters, modify the received uplink packet, and forward the modified uplink packet to the next hop in the path towards the destination IP address in response to determining that the packet is enqueued successfully.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 17, 2025
    Inventors: Feilu LIU, Suli ZHAO, Siddharth GUPTA, Alok MITRA
  • Patent number: 12277028
    Abstract: An apparatus comprises a storage configured to store data items associated with error correction codes (ECCs); data retrieval circuitry responsive to a data retrieval request specifying a retrieval address to retrieve a retrieved data item and an associated ECC from a storage location corresponding to the retrieval address; and ECC decoding circuitry to generate a syndrome value by performing an ECC decoding operation on a decoding input value comprising data bits of the retrieved data item, code bits of the associated ECC, and address bits of the retrieval address, and to determine based on the syndrome value whether an error condition has occurred. Each bit of the syndrome value depends on a different combination of bits of the decoding input value. For each data bit of the decoding input value, an odd number of bits of the syndrome value depend on that data bit. For each address bit of the decoding input value, an even number of bits of the syndrome value depend on that address bit.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: April 15, 2025
    Assignee: Arm Limited
    Inventors: Siddharth Gupta, Antony John Penton
  • Publication number: 20250045155
    Abstract: An apparatus comprises a storage configured to store data items associated with error correction codes (ECCs); data retrieval circuitry responsive to a data retrieval request specifying a retrieval address to retrieve a retrieved data item and an associated ECC from a storage location corresponding to the retrieval address; and ECC decoding circuitry to generate a syndrome value by performing an ECC decoding operation on a decoding input value comprising data bits of the retrieved data item, code bits of the associated ECC, and address bits of the retrieval address, and to determine based on the syndrome value whether an error condition has occurred. Each bit of the syndrome value depends on a different combination of bits of the decoding input value. For each data bit of the decoding input value, an odd number of bits of the syndrome value depend on that data bit. For each address bit of the decoding input value, an even number of bits of the syndrome value depend on that address bit.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Siddharth GUPTA, Antony John PENTON
  • Publication number: 20250045154
    Abstract: An apparatus comprising: a storage configured to store data items; and address digest generating circuitry responsive to a request to store a received data item to a location of the storage associated with a store target address, to generate an address digest based on a plurality of bits of the store target address, the address digest having fewer bits than the plurality of bits. The storage is configured to store the address digest in association with the received data item.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Siddharth GUPTA, Antony John PENTON