Abstract: An electronic device includes a stack assembly and a cover glass. The stack assembly includes an electronic paper display sub-assembly for rendering content, a front light sub-assembly for illuminating the electronic display sub-assembly, and a capacitive touch sensing sub-assembly for detecting touch inputs. The cover glass includes two apertures for the placement of control buttons for the electronic device. Prior to assembly of the electronic device, the cover glass is strengthened after the two apertures are formed so as to strengthen the interior edges of the apertures.

Abstract: Systems, methods, devices, and non-transitory processor-readable storage media of the various embodiments enable a software enabled access point (“softAP”) computing device to route evolved Multimedia Broadcast Multicast Service (“eMBMS”) multicast (“MCAST”) traffic to connected local area network (“LAN”) client devices. In an embodiment, a self-assigned Internet Protocol (“IP”) address may be assigned to the wide area network (“WAN”) interface of the softAP computing device where eMBMS MCAST traffic may be received and an MCAST routing daemon/utility of the softAP computing device may enable MCAST forwarding from the WAN interface to the LAN interface of the softAP computing device. In an embodiment, an MCAST routing daemon/utility may be modified to accept an alternate network comprising all source IP addresses.

Abstract: The subject matter disclosed herein relates to an electrowetting display comprising pixels that include colored subpixels that comprise: a colored reflective layer on a support plate; an electrode; a hydrophobic layer; and a liquid region including an electrolyte, and dark electrowetting oil and white electrowetting oil both being immiscible with the electrolyte. A coverage area of the dark electrowetting oil on the hydrophobic layer and a coverage area of the white electrowetting oil on the hydrophobic layer are individually electronically adjustable to affect light transmission to the colored reflective material.

Abstract: A display includes a lightguide having an array of light extraction features that can be actively controlled to direct varying amounts of light received from one or more light sources arranged at the edge of the display. The light extraction features include two fluids with different refractive indices. The relative positions of the fluids in each light extraction feature are controlled, e.g., by electrowetting, to control the amount of light directed toward the display.

Abstract: Techniques for providing visual feedback on a display of an electronic device by sequentially and/or independently controlling the illumination of the lighting output by the display. In some implementations, the techniques may be employed following an interaction with the device having one or more light source controllers instructing one or more light sources, such as Light Emitting Diodes (LEDs), in a lighting apparatus, such as for a display which renders content on the device. For instance, a lightguide of the lighting apparatus may sequentially receive light from the one or more light sources as directed by the one or more light source controllers and may direct the light to provide illumination for a display. In some cases, the display may be a reflective display that is front-lit by the lighting apparatus. In other cases, the display may be a backlit display that is backlit by the lighting apparatus.

Abstract: Methods and devices are disclosed where a voltage on a wordline is changed from a first voltage to a second voltage via a plurality of intermediate voltages.

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus may be a network device. The apparatus receives an evolved multimedia broadcast multicast service (eMBMS) data from a base station via multicast transmission. The apparatus transmits the received eMBMS data to one or more end nodes via unicast transmission. In an aspect, the one or more end nodes are connected to the network device via a local area network (LAN).

Abstract: This disclosure describes electronic devices that include displays for rendering content, touch sensors disposed beneath the displays for detecting touch inputs, and antiglare components for reducing glare caused by ambient light. In some embodiments, the displays include a single transparent substrate, a thin film transistor array connected to a bottom surface of the transparent substrate, a conductive substrate, and a front plane laminate connected to the conductive substrate. In such embodiments, the front plane laminate is connected to the thin film transistor array, and the array comprises a plurality of transparent electrodes. This disclosure also describes techniques for manufacturing displays utilized with electronic devices.

Abstract: A front light component for electronic devices that include displays for rendering content using a light guide to control illumination for a front light display. A high reflectivity “white” tape is used under and adjacent to the light guide to improve overall uniformity of the light beams. The high reflectivity tape may also be selected to be of a controlled white hue to compensate for variances in color of Light Emitting Diodes (LEDs) where the LED color is slightly off from ideal white. In this way the complementary color of the high reflectivity tape with the color of the LED will cause the output spectrum to be uniform and white. This disclosure also describes techniques for assembling electronic devices in a component stack to provide enhanced display uniformity and improved reading experience.

Abstract: Methods and devices are disclosed where a voltage on a wordline is changed from a first voltage to a second voltage via a plurality of intermediate voltages.

Abstract: A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: A memory arrangement, particularly a ROM, having memory cells, local virtual supply voltage lines, word lines and result lines may also include global virtual supply voltage lines that run along the width of the memory arrangement parallel to the word lines. The local virtual supply voltage lines run parallel to the result lines, and perpendicularly to the word lines where the each local virtual supply voltage line runs only within a block of the memory arrangement. Each global virtual supply voltage line, in each block through which it runs, is connected to one local virtual supply voltage line. The coupling capacitance between the supply voltage lines and the result lines, and the inherent capacitance of the supply voltage lines are reduced, reducing the power consumption and increasing the clock frequency of the memory arrangement.

Abstract: A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference section for the third core memory array and the fourth core memory array. Another memory device with shared signals and a method is also provided.