Patents by Inventor Sidlgata V. Sreenivasan

Sidlgata V. Sreenivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210366771
    Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
    Type: Application
    Filed: December 21, 2018
    Publication date: November 25, 2021
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Ovadia Abed, Mark McDermott, Jaydeep Kulkarni, Shrawan Singhal
  • Publication number: 20210350061
    Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.
    Type: Application
    Filed: September 6, 2019
    Publication date: November 11, 2021
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Jaydeep Kulkarni
  • Publication number: 20210341833
    Abstract: A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.
    Type: Application
    Filed: August 3, 2017
    Publication date: November 4, 2021
    Inventors: Sidlgata V. Sreenivasan, Shrawan Singhal, Ovadia Abed, Lawrence Dunn, Paras Ajay, Ofodike Ezekoye
  • Patent number: 11020894
    Abstract: Control of lateral strain and lateral strain ratio (dt/db) between template and substrate through the selection of template and/or substrate thicknesses (Tt and/or Tb), control of template and/or substrate back pressure (Pt and/or Pb), and/or selection of material stiffness are described.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 1, 2021
    Assignee: Molecular Imprints, Inc.
    Inventors: Se-Hyuk Im, Mahadevan GanapathiSubramanian, Edward Brian Fletcher, Niyaz Khusnatdinov, Gerard M. Schmid, Mario Johannes Meissl, Anshuman Cherala, Frank Y. Xu, Byung Jin Choi, Sidlgata V. Sreenivasan
  • Publication number: 20210134640
    Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 6, 2021
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Mark McDermott, Shrawan Singhal, Ovadia Abed, Lawrence Dunn, Vipul Goyal, Michael Cullinan
  • Publication number: 20200365464
    Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 19, 2020
    Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
  • Patent number: 10717646
    Abstract: A method and alignment system for minimizing errors in the deposition of films of tailored thickness. A first position on a stage is identified for optimal placement of a downward looking microscope (DLM) and an upward looking microscope (ULM) when alignment marks on the DLM and ULM are aligned, where the DLM is attached to a bridge and the ULM is attached to the stage. A second position on the stage is identified when the ULM on the stage is aligned with the alignment marks on a metrology tool. A surface of a chucked substrate affixed to the stage is then measured. A map between a substrate coordinate system and a metrology coordinate system may then be obtained using the measured surface of the chucked substrate with the first and second positions.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: July 21, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Shrawan Singhal
  • Publication number: 20200105154
    Abstract: A portable system to enable broad access to micro- and nano-scale technologies. The portable system includes a fabrication module configured to enable creation of a small tech device or structure or to enable demonstration of a small tech process. The portable system further includes a metrology module configured to allow measuring, testing or characterizing a property of the small tech device, structure or process. Furthermore, the portable system includes a quality control module configured to validate results from the metrology module against a set of expected results measured independently. The portable system is used for the design and assembly of a prototype tool with all the functionalities or a subset of functionalities present in a master tool used in a small tech factory.
    Type: Application
    Filed: May 16, 2018
    Publication date: April 2, 2020
    Inventors: Sidlgata V. Sreenivasan, Ovadia Abed, Lawrence R. Dunn, Aseem Sayal, Shrawan Singhal
  • Patent number: 10578964
    Abstract: Systems and methods for partial field imprinting are provided such that imprint templates are asymmetrically modulated to allow initial contact with a partial field on a substrate at a location spaced apart from the template center.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: March 3, 2020
    Assignee: Canon Nanotechnologies, Inc.
    Inventors: Mahadevan Ganapathisubramanian, Matthew M. Kincaid, Byung-Jin Choi, Sidlgata V. Sreenivasan
  • Publication number: 20190139456
    Abstract: A portable system to enable broad access to micro- and nano-scale technologies. The portable system includes a fabrication module configured to enable creation of a small tech device or structure or to enable demonstration of a small tech process. The portable system further includes a metrology module configured to allow measuring, testing or characterizing a property of the small tech device, structure or process. Furthermore, the portable system includes a quality control module configured to validate results from the metrology module against a set of expected results measured independently.
    Type: Application
    Filed: March 21, 2017
    Publication date: May 9, 2019
    Inventors: Sidlgata V. Sreenivasan, Shrawan Singhal, Ovadia Abed, Lawrence Dunn, Aseem Sayal, Benjamin Eynon
  • Publication number: 20190061228
    Abstract: Control of lateral strain and lateral strain ratio (dt/db) between template and substrate through the selection of template and/or substrate thicknesses (Tt and/or Tb), control of template and/or substrate back pressure (Pt and/or Pb), and/or selection of material stiffness are described.
    Type: Application
    Filed: October 30, 2018
    Publication date: February 28, 2019
    Inventors: Se-Hyuk Im, Mahadevan GanapathiSubramanian, Edward Brian Fletcher, Niyaz Khusnatdinov, Gerard M. Schmid, Mario Johannes Meissl, Anshuman Cherala, Frank Y. Xu, Byung Jin Choi, Sidlgata V. Sreenivasan
  • Patent number: 10191368
    Abstract: Techniques for delivering sub-5 nm overlay control over multiple fields. One such technique reduces overlay from the wafer side using wafer-thermal actuators. In another technique, the topology of the template is optimized so that the inter-field mechanical coupling between fields in the multi-field template is reduced thereby allowing overlay to be simultaneously reduced in multiple fields in the template. A further technique combines the wafer-thermal and template actuation techniques to achieve significantly improved single and multi-field overlay performance.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: January 29, 2019
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Anshuman Cherala
  • Patent number: 10026609
    Abstract: A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub-10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: July 17, 2018
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Anshuman Cherala, Meghali Chopra, Roger Bonnecaze, Ovadia Abed, Bailey Yin, Akhila Mallavarapu, Shrawan Singhal, Brian Gawlik
  • Patent number: 9987653
    Abstract: A method for depositing thin films using a nominally curved substrate. Drops of a pre-cursor liquid organic material are dispensed at a plurality of locations on a nominally curved substrate by one or more inkjets. A superstrate is brought down on the dispensed drops to close the gap between the superstrate and the substrate thereby allowing the drops to form a contiguous film captured between the substrate and the superstrate. A non-equilibrium transient state of the superstrate, the contiguous film and the substrate is enabled to occur after a duration of time. The contiguous film is then cured to solidify it into a solid. The solid is separated from the superstrate thereby leaving a polymer film on the substrate. In this manner, such a technique for film deposition has the film thickness range, resolution and variation required to be applicable for a broad spectrum of applications.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: June 5, 2018
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Shrawan Singhal
  • Patent number: 9972699
    Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: May 15, 2018
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
  • Patent number: 9972698
    Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: May 15, 2018
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
  • Patent number: 9941389
    Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: April 10, 2018
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
  • Publication number: 20170333940
    Abstract: A method and alignment system for minimizing errors in the deposition of films of tailored thickness. A first position on a stage is identified for optimal placement of a downward looking microscope (DLM) and an upward looking microscope (ULM) when alignment marks on the DLM and ULM are aligned, where the DLM is attached to a bridge and the ULM is attached to the stage. A second position on the stage is identified when the ULM on the stage is aligned with the alignment marks on a metrology tool. A surface of a chucked substrate affixed to the stage is then measured. A map between a substrate coordinate system and a metrology coordinate system may then be obtained using the measured surface of the chucked substrate with the first and second positions.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 23, 2017
    Inventors: Sidlgata V. Sreenivasan, Shrawan Singhal
  • Patent number: 9778562
    Abstract: An imprint lithography template or imprinting stack includes a porous material defining a multiplicity of pores with an average pore size of at least about 0.4 nm. A porosity of the porous material is at least about 10%. The porous template, the porous imprinting stack, or both may be used in an imprint lithography process to facilitate diffusion of gas trapped between the template and the imprinting stack into the template, the imprinting stack or both, such that polymerizable material between the imprinting stack and the template rapidly forms a substantially continuous layer between the imprinting stack and the template.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: October 3, 2017
    Assignee: Canon Nanotechnologies, Inc.
    Inventors: Frank Y. Xu, Weijun Liu, Edward Brian Fletcher, Sidlgata V. Sreenivasan, Byung Jin Choi, Niyaz Khusnatdinov, Anshuman Cherala, Kosta S. Selinidis
  • Patent number: RE47483
    Abstract: A nanoimprint lithography template including, inter alia, a body having first and second opposed sides with a first surface disposed on the first side, the second side having a recess disposed therein, the body having first and second regions with the second region surrounding the first region and the recess in superimposition with the first region, with a portion of the first surface in superimposition with the first region being spaced-apart from the second side a first distance and a portion of the first surface in superimposition with the second region being spaced-apart from the second side a second distance, with the second distance being greater than the first distance; and a mold disposed on the first side of the body in superimposition a portion of the first region.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: July 2, 2019
    Assignees: Molecular Imprints, Inc., Canon Nanotechnologies, Inc.
    Inventors: Douglas J. Resnick, Mario Johannes Meissl, Byung-Jin Choi, Sidlgata V. Sreenivasan