Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: A method and system for etching a semiconductor substrate using catalyst influenced chemical etching. A group of independently controlled discrete actuators are configured to control a depth of an etch of a material on a substrate, where at least two of the group of independently controlled discrete actuators has distinct actuation values. Furthermore, the etch depth has a variation of less than 10% of a feature height across the substrate.

Abstract: A method for introducing a customized variation of a geometric parameter in a nanoscale pattern on a substrate. A nanoscale precision programmable profiling process is conducted on one or more regions of the substrate with the nanoscale pattern, where the nanoscale precision programmable profiling process is used to deposit a profiling film with a thickness profile that is a function of the customized variation of the geometric parameter in the nanoscale pattern. The method further comprises conducting a plasma etch process of the profiling film and the material of the nanoscale pattern that converts the thickness profile of the profiling film into the customized variation of the geometric parameter in the nanoscale pattern, where the customized variation is a function of the thickness profile of the profiling film.

Abstract: A method for fabricating patterns. An inverse optimization scheme is implemented to determine process parameters used to obtain a desired film thickness of a liquid resist formulation, where the liquid resist formulation includes a solvent and one or more non-solvent components. A substrate is covered with a substantially continuous film of the liquid resist formulation using one or more of the following techniques: dispensing discrete drops of a diluted monomer on the substrate using an inkjet and allowing the dispensed drops to spontaneously spread and merge, slot die coating and spin-coating. The liquid resist formulation is diluted in the solvent. The solvent is then substantially evaporated from the liquid resist formulation forming a film. A gap between a template and the substrate is then closed. The film is cured to polymerize the film and the substrate is separated from the template leaving the polymerized film on the substrate.

Abstract: A diagnostic chip for detecting biomarkers and trace amounts of nanoparticles in chemical mixtures or in water. The diagnostic chip includes one or more inputs, where a sample containing differently sized particles is introduced into at least one of these inputs. Furthermore, the diagnostic chip includes multiple separation regions, where the sample is pressurized as it passes through the separation regions. Each separation region includes a deterministic lateral displacement array, where the deterministic lateral displacement array in two or more of these separation regions has a different etch depth profile. In this manner, the diagnostic chip effectively detects biomarkers and trace amounts of nanoparticles in chemical mixtures or in water.

Abstract: A method for bonding with precision alignment. A first bonding surface is bonded with a second bonding surface, where features on the first and second bonding surfaces are precisely overlaid during the bonding. An etch is then performed on the first and/or second bonding surfaces to create recesses in the first and/or second bonding surfaces. Precision alignment of the first and second bonding surfaces is then enabled by a volatile fluid deployed between the first and second bonding surfaces, where the recesses enable removal of the volatile fluid from a bonding interface during and after the bonding.

Abstract: A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.

Abstract: A method for fabricating one or more elements in a multi-lens column. Drops of ultraviolet (UV)-curable liquid are dispensed by an inkjet on a substrate, which may be supported by a chuck. A non-uniform liquid film is then formed, such as by spreading and merging of the inkjetted drops. The film is then locally heated, such as by using a digital micromirror device array. The film is then cured by exposing it to UV light, where the cured film together with the substrate form an element of the multi-lens column. The substrate is then brought to a metrology station where optical metrology is performed on the cured film and the substrate for quality control.

Abstract: A method for fabricating silicon nanostructures. An etch uniformity improving layer is deposited on a substrate. A catalyst (e.g., thin film of Ti/Au) is deposited on the substrate or the etch uniformity improving layer, where the catalyst is contacting a portion of the substrate or the etch uniformity layer. The catalyst and the substrate or etch uniformity improving layer are exposed to an etchant, where the catalyst causes etching of the substrate thereby creating etched nanostructures.

Abstract: A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method, computer program product and system for precision inkjet printing. A control variable vector of actuation parameters associated with an inkjet waveform is determined. A printhead is then actuated to eject a grid of droplets from an inkjet onto a substrate based on the inkjet waveform. An image of the grid of droplets on the substrate is acquired. The acquired image is then processed to calculate a fitness function of the inkjet waveform that includes a function of sensed output variables associated with printing characteristics. The control variable vector is then adjusted by updating its topology based on the fitness function to obtain an optimized control variable vector associated with an optimized inkjet waveform.

Abstract: A method and system for nanoscale precision programmable profiling on substrates. Profiling material is dispensed on a substrate or a superstrate. The superstrate is brought in contact with the substrate. The profiling material is then cured after bringing the superstrate in contact with the substrate. The superstrate is separated from the substrate after curing. An optical metrology of points on the substrate corresponding to the final substrate profile is then performed.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.