Abstract: A vertical pair of complementary, bipolar transistors is disclosed which includes a semiconductor substrate of one conductivity type and a pair of dielectric isolation regions disposed in contiguous relationship with the substrate. An injector region of opposite conductivity type is disposed between the pair of isolation regions. A pair of heavily doped, polycrystalline, semiconductor regions of the one conductivity type is disposed over and in registry with the pair of isolation regions. Similarly, a single crystal, semiconductor region of the one conductivity type is disposed over and in registry with the injector region. Finally, a first zone of opposite conductivity type is disposed in the single crystal region and a second zone of the one conductivity type is disposed in the first zone.

Abstract: The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I.sup.2 L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I.sup.2 L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance.

Abstract: A Schottky diode structure and self-aligned fabrication method wherein the cathode or ohmic contact is disposed in the center of the anode or Schottky contact and is isolated therefrom by an overlapping layer of insulation. This structure has a reduced area size; it allows the use of only one metal line for both anode contacts and affords a marked advantage of device density. The structure includes a substrate having an n+ sub-diffusion therein, an epitaxial layer over the sub-diffusion which serves as the cathode electrode of the Schottky barrier device, and recessed oxide regions on the substrate for isolation. A heavily doped n+ polysilicon layer is disposed over the epitaxial layer and is used as a source of impurities for the diffusion which makes contact to the Schottky barrier diode. The structure is masked and exposed by conventional photolithographic or electron-beam techniques and is etched down to the epitaxial layer leaving a strip of n+ polysilicon.

Abstract: The invention relates to a monolithically integrated storage cell which includes a flip-flop circuit with two cross-coupled, bipolar switching transistors and one load element each connected by means of one terminal to the collectors of the switching transistors, the storage cell being controlled via a word line connected to the other terminal of both load elements and via one bit line each of a bit line pair connected to the emitter of each switching transistor.

Abstract: The disclosure is directed to the circuitry and monolithic semiconductor structure of Current Hogging Injection Logic Configurations. More specifically the disclosure relates to a semiconductor arrangement for the basic components of a highly integratable, logic semiconductor circuit concept predicated on multicollector inverter transistors which are fed by means of a carrier injection into their emitter/base zones.

Abstract: This teaches a sense circuit for an integrated memory storage system in which the storage cell output is detected by a differential amplifier, controlling a flip-flop, serving as a latch, having load elements which also function as the load elements of the latch to ensure an optimum power and speed product. The latch can be coupled to an output driver circuit through a current switch which shares common elements with the latch to assure that the latch remains symmetrical even when used with an output driver having asymmetrical control.

Abstract: Modern bipolar cross coupled memory cells for high density arrays use diodes as coupling elements from the cell to the bit lines. The write operation of these cells requires a high amount of current if the current gain of the cell transistors is high. The time required to perform a write operation is prolonged significantly due to the inherent capacitors in the cell known as the Miller effect. The described circuit completely eliminates the Miller effect during the write operation and makes the required write current completely independent of the current gain of the cell transistors.In the present invention this is accomplished by dropping the word line of such a cell from a stand-by potential to a select potential, so that the inner cell nodes are equally discharged, without disturbing the state of the cell, after which the word line is pulsed up to an intermediate potential between the select potential and the stand-by potential.

Abstract: A method and circuit arrangement for operating an information store, in particular a monolithic information store, whose storage cells and address circuits comprise bipolar transistors which are not continuously subjected to full power. The monolithic information store is readily fabricated by known planar process technology, has increased density, has reduced read/write times, reduced cycle time, and reduced power dissipation.

Abstract: Integrated circuit devices for carrying out boolean logic functions of at least two input variables.The integrated circuit device for carrying out the logical function of at least two input variables is characterized as follows: the transistors employed are bipolar transistors of a first conductivity type and of a second conductivity type opposite to said first conductivity type; the input variables are coupled respectively to the control electrodes of a first transistor of said first conductivity type, and of a second transistor of said second conductivity type provided in the load branch of said first transistor; said bipolar transistors of said first conductivity type and of said second conductivity type having essentially symmetrical switching characteristics, particularly their current gain factors in normal and inverted direction.For a NOR or NAND function first bipolar transistors arranged in series or parallel, of the one conductivity type, e.g.

Abstract: A complementary field effect transistor structure which eliminates the problems caused by parasitic currents between devices. The currents are contained within parasitic bipolar devices formed between the various regions of the FETs. A portion of the collector current of the parasitic bipolar devices is drained away so that the loop gain is less than one. This is achieved by placing guard regions of conductivity type which are the same as the channel type of the transistors adjacent said regions. The guard region is preferably in the form of a continuous ring around its associated FET.

Abstract: to prevent a parasitic lateral transistor or thyristor effect in an integrated structure including a transistor and a further device sharing one common zone, a doped region which is more highly doped with regard to the common zone and which simultaneously constitutes a contact region is arranged between the components to be separated. This separating and contact region acts as a barrier reflecting an undesired minority carrier current flow injected from the further device. In the preferred embodiment, the transistor structure is a bipolar transistor and the further semiconductor device is a Schottky diode integrated into the collector zone of the bipolar transistor.