Abstract: A user environment for a multi-user collaborative data governance system. The user-environment includes one or more data connectors, one or more data catalogs, one or more datasets, and a user environment service. A multi-user collaborative data governance method implemented on one or more processors includes associating each of one or more datasets with a data item from one of one or more data connectors and associating each of the one or more datasets with a subscribed data item subscribed from one of one or more data catalogs. Further steps are associating each of the one or more datasets with a published dataset in one of the one or more data catalogs through publishing the dataset on the data catalog and associating each of one or more collaborators with one or more datasets with usage permission.

Abstract: Disclosed is a system for inter-sharing of data among a plurality of data users, which may include a virtual dataset service subsystem, configured to: in response to a data access request initiated by a data user or an application of the data user to a dataset, determine an original dataset associates to the dataset, create a virtual dataset associated with the original dataset, and return the created virtual dataset. Embodiments of the present disclosure also provide a method for inter-sharing of data among a plurality of data users, a computing device and a non-transitory computer-readable storage medium.

Abstract: Aspects of the disclosure provide a circuit that includes a switch, a current path circuit and a control circuit. The switch is turned on/off to direct a power supply with a periodic varying voltage to the current path circuit. The current path circuit is coupled with the switch in series to provide a discharge current path to the power supply. The control circuit is configured to detect a time duration during which the periodic varying voltage decreases, and turn on the switch during the time duration to provide the discharge current path to the power supply.

Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block.

Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block.

Abstract: A system including a switch and a control circuit. The switch is configured to receive a first voltage. The control circuit is configured to, during a rising portion of a half cycle of the first voltage, (i) turn on the switch in response to the first voltage reaching a first value, and (ii) turn off the switch in response to the first voltage reaching a second value, where the second value is greater than the first value. The control circuit is further configured to, during a falling portion of the half cycle of the first voltage, (i) turn on the switch in response to the first voltage reaching the second value, and (ii) turn off the switch in response to the first voltage reaching the first value.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a depletion mode transistor coupled to a power supply and a current path coupled with the depletion mode transistor in series to provide a current to charge a capacitor. The current path has a first resistance during a first stage, such as when the circuit initially receives power, and has a second resistance during a second stage when the capacitor is charged to have a predetermined voltage level.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a transistor configured to control energy entering the circuit from a power supply, a capacitor coupled with the transistor to store the energy that enters the circuit, and a protection circuit configured to counteract a voltage change of the transistor that is caused by a step voltage change in the power supply. In an embodiment, the protection circuit operates independent of the stored energy on the capacitor.

Abstract: A multi-converter system includes a first converter configured to receive an input voltage and output a first PWM switching signal based on the input voltage. A power distribution balancing circuit is configured to detect a frequency of the first PWM switching signal and generate a control signal based on the frequency of the first PWM switching signal. A second converter is configured to receive the input voltage and output a second PWM switching signal in response to the control signal. An output voltage node is configured to output an output voltage based on the first and second PWM switching signals.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a control circuit and a return path circuit. The control circuit is configured to operate in response to a first conduction angle of a dimmer coupled to the circuit. The first conduction angle is adjusted to control an output power to a first device. The dimmer has a second conduction angle that is independent of the control of the output power to the first device. The return path circuit is configured to provide a return path to enable providing power to a second device in response to the second conduction angle.

Abstract: Aspects of the disclosure provide a circuit that can include a depletion mode transistor coupled to a power source and a current path coupled with the depletion mode transistor in series to provide a current to charge a capacitor. Further, a gate terminal of the depletion mode transistor is coupled to a clamping path that includes a diode and a switch that connected in series. The clamping path clamps the voltage at the gate terminal of the depletion mode transistor to the capacitor. The clamping and the current paths respectively have a first resistance during a first stage, such as when the circuit initially receives power, and have a second resistance during a second stage when the capacitor is charged to have a predetermined voltage level.

Abstract: The present invention provides a distributed clustering method to allow multiple active instances of consistency management processes that apply the same encoding scheme to be cooperative and function collectively. The techniques described herein facilitate an efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. The technique can be applied on many forms of distributed persistent data stores to provide failure resiliency and to maintain data consistency and correctness.

Abstract: An integrated circuit including a well region, a plurality of semiconductor regions implanted in the well region, and a plurality of polysilicon regions arranged on each of the plurality of semiconductor regions. The well region has a first doping level. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. The polysilicon regions are respectively connected directly to the plurality of semiconductor regions.

Abstract: A circuit for driving a transistor includes a drive circuit, a first voltage boost circuit and a second voltage boost circuit. The drive circuit has a first specific node, a second specific node, and a third specific node coupled to a control node of the transistor. The drive circuit is arranged for coupling the first specific node to the third specific node according to at least a voltage of the first specific node and a voltage of the second specific node in order to charge the control node. The first voltage boost circuit is coupled between the first specific node and a connection node of the transistor, and is arranged for boosting the voltage of the first specific node. The second voltage boost circuit is coupled between the first specific node and the second specific node, and is arranged for boosting the voltage of the second specific node.

Abstract: A method is integrated into the local operating system of a test machine. The disclosed technique preferably uses a master copy of one or more data objects from a first location to create virtual data objects (e.g., files or folders) that appear to be part of a file system mounted to a test machine in a second location. This disclosure describes a “projection” method and computer program that enables access to a destination object at a target location immediately upon initiation of a copy command at a source location while a copy operation is carried out in a background manner.

Abstract: A linear regulator includes a first drive voltage output to drive an analog load, a second drive voltage output to drive a digital load, and a third output to provide a clean source of current. Circuit elements that produce the respective drive voltages may be isolated from each other. In addition, local feedback may be included to compensate for wide swings in circuit loading conditions in the analog load and in the digital load.

Abstract: An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET).

Abstract: A data management system (DMS) includes a continuous real-time object store that captures all real-time activities, with associated object metadata information. The DMS is capable of reintroducing any point-in-time view of data ranging from a granular object to an entire file system. A set of algorithms (for creation of a file or directory, modification of a file or directory, deletion of a file or directory, and relocation/renaming of a file or directory) are used to generate and maintain a file system history in the DMS and to ensure that a latest version of a directory always refers to a latest version of its children until the directory changed. Any point-in-time recovery is implemented using the file system history in one of various ways to provide strong individual file integrity, exact point-in-time crash consistency, and/or recovery of last version of all files in the file system.

Abstract: Aspects of the disclosure provide a circuit. The circuit includes a depletion mode transistor coupled to a power supply and a current path coupled with the depletion mode transistor in series to provide a current to charge a capacitor. The current path has a first resistance during a first stage, such as when the circuit initially receives power, and has a second resistance during a second stage when the capacitor is charged to have a predetermined voltage level.

Abstract: A circuit for driving a transistor includes a drive circuit, a first voltage boost circuit and a second voltage boost circuit. The drive circuit has a first specific node, a second specific node, and a third specific node coupled to a control node of the transistor. The drive circuit is arranged for coupling the first specific node to the third specific node according to at least a voltage of the first specific node and a voltage of the second specific node in order to charge the control node. The first voltage boost circuit is coupled between the first specific node and a connection node of the transistor, and is arranged for boosting the voltage of the first specific node. The second voltage boost circuit is coupled between the first specific node and the second specific node, and is arranged for boosting the voltage of the second specific node.