Abstract: An array switch circuit system includes a substrate, a plurality of first conductive pads, a plurality of first row/column switches, a plurality of second conductive pads and a plurality of first transmission lines. The first conductive pads are spaced apart from each other on the substrate and arranged as an array. Each of the first conductive pads has a column/row position in the array. Each of the first column/row switches connects two adjacent ones of the first conductive pad corresponding to the same column/row position. The plurality of second conductive pads are disposed on a periphery of the first conductive pad. Each of the first transmission lines connects two of the second conductive pads, and includes a first conductor strip and two second conducting strips. The two second conducting strips are respectively located on both sides of the first conducting strip and are coplanar with the first conducting strip.

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

Abstract: An all-oxide transistor structure includes a substrate, a first transistor, a second transistor, a third transistor and a fourth transistor. The substrate has an upper surface. The first transistor is disposed on the upper surface of the substrate. The second transistor is disposed on the upper surface of the substrate, wherein the second transistor is electrically connected to the first transistor. The third transistor is electrically connected to the second transistor and overlapped with the second transistor in a first direction, wherein the first direction is parallel to a normal direction of the upper surface of the substrate. The fourth transistor is disposed on the upper surface of the substrate, wherein the fourth transistor is electrically connected to the first transistor, the second transistor and the third transistor.

Abstract: A switching circuit includes a transmission gate, two base control sub-circuits each including a first transistor and a second transistor, a third transistor, and a fourth transistor. The transmission gate includes two I/O terminals, two gate control terminals, and two base control terminals, and is configured to conduct or not conduct the two I/O terminals according to the voltage of the two gate control terminals. The two base voltage control sub-circuits, the third transistor and the fourth transistor forms a double balance circuit structure and is electrically connected to the transmission gate. The double balance circuit changes the voltage of the base control terminals according to the voltage of the I/O terminals of the transmission gate.

Abstract: A high-frequency component test device including a test key and a test module is provided. The test key includes a front-level key and a back-level key which are arranged symmetrically and have the same electrical length and characteristic impedance. The test module is used to measure an S parameter of the front-level key and the back-level key connected directly and an S parameter of a structure where a device under test (DUT) is added between the front-level key and the back-level key. The test module performs S parameter calculation in the frequency domain and converts the S parameter into an ABCD parameter matrix, and then obtains an ABCD parameter of a de-embedded DUT using a matrix root-opening operation and an inverse matrix operation.

Abstract: A high-frequency component test device including a test key and a test module is provided. The test key includes a front-level key and a back-level key which are arranged symmetrically and have the same electrical length and characteristic impedance. The test module is used to measure an S parameter of the front-level key and the back-level key connected directly and an S parameter of a structure where a device under test (DUT) is added between the front-level key and the back-level key. The test module performs S parameter calculation in the frequency domain and converts the S parameter into an ABCD parameter matrix, and then obtains an ABCD parameter of a de-embedded DUT using a matrix root-opening operation and an inverse matrix operation.

Abstract: An arrayed switch circuit includes a substrate, signal conductive pads and signal expansion pins. The signal conductive pads are disposed on the substrate at intervals, and the signal conductive pads are arranged to form a signal conductive pad array. Each of the signal conductive pads has a row position and a column position in the signal conductive pad array. A row signal switch is provided between any two adjacent signal conductive pads corresponding to the same row position, and a column signal switch is provided between any two adjacent signal conductive pads corresponding to the same column position. The signal expansion pins are connected to the signal conductive pads located on at least one side of the signal conductive pad array through signal expansion switches respectively.

Abstract: A switching circuit includes a transmission gate, two base control sub-circuits each including a first transistor and a second transistor, a third transistor, and a fourth transistor. The transmission gate includes two I/O terminals, two gate control terminals, and two base control terminals, and is configured to conduct or not conduct the two I/O terminals according to the voltage of the two gate control terminals. The two base voltage control sub-circuits, the third transistor and the fourth transistor forms a double balance circuit structure and is electrically connected to the transmission gate. The double balance circuit changes the voltage of the base control terminals according to the voltage of the I/O terminals of the transmission gate.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

Abstract: A configurable computing unit within memory including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor is provided. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first readout bit line and a common signal line. The first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first readout bit line and the common signal line. The second input transistor is coupled to a second input bit line, and the second weight transistor receives the second weight bit.

Abstract: An arrayed switch circuit includes a substrate, signal conductive pads and signal expansion pins. The signal conductive pads are disposed on the substrate at intervals, and the signal conductive pads are arranged to form a signal conductive pad array. Each of the signal conductive pads has a row position and a column position in the signal conductive pad array. A row signal switch is provided between any two adjacent signal conductive pads corresponding to the same row position, and a column signal switch is provided between any two adjacent signal conductive pads corresponding to the same column position. The signal expansion pins are connected to the signal conductive pads located on at least one side of the signal conductive pad array through signal expansion switches respectively.

Abstract: A high-frequency component test device including a test key and a test module is provided. The test key includes a front-level key and a back-level key which are arranged symmetrically and have the same electrical length and characteristic impedance. The test module is used to measure an S parameter of the front-level key and the back-level key connected directly and an S parameter of a structure where a device under test (DUT) is added between the front-level key and the back-level key. The test module performs S parameter calculation in the frequency domain and converts the S parameter into an ABCD parameter matrix, and then obtains an ABCD parameter of a de-embedded DUT using a matrix root-opening operation and an inverse matrix operation.

Abstract: An arrayed switch circuitry includes contact units each of which includes a pad, a first row channel provided with a first switching element, a first column channel connected to the first row channel and provided with a second switching element, a connecting channel connecting the pad to the first row channel or the first column channel, a second row channel connected with the pad through a third switching element and a second column channel connected with the pad through a fourth switching element. The first row channels with the same row position are connected to each other, and the second row channels with the same row position are connected to each other. The first column channels with the same column position are connected to each other, and the second column channels with the same column position are connected to each other.

Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.

Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.

Abstract: A position-encoding device includes a sensing device, a filtering device, a calibrating device and a compensating device. The sensing device senses the motion of a moving device to generate first and second signals. The filtering device filters the first and second signals to generate first and second filtering signal. The calibrating device captures the first and second filtering signals to obtain time and phase information of the first and second filtering signals, performs gain and offset calibration on the first and second filtering signals, and performs a phase calibration on the first and second filtering signals through first, second feedback signals and the time and phase information of the first and second filtering signals to generate first and second calibrating signals. The compensating device compensates for the first and second calibrating signals according to a lookup table, so as to generate first and second position encoding signals.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.