Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

Abstract: A configurable computing unit within memory including a first input transistor, a first weight transistor, a first resistor, a second input transistor, a second weight transistor, and a second resistor is provided. The first input transistor, the first weight transistor, and the first resistor are coupled in series between a first readout bit line and a common signal line. The first input transistor is coupled to a first input bit line, and the first weight transistor receives a first weight bit. The second input transistor, the second weight transistor, and the second resistor are coupled in series between the first readout bit line and the common signal line. The second input transistor is coupled to a second input bit line, and the second weight transistor receives the second weight bit.

Abstract: A high-frequency component test device including a test key and a test module is provided. The test key includes a front-level key and a back-level key which are arranged symmetrically and have the same electrical length and characteristic impedance. The test module is used to measure an S parameter of the front-level key and the back-level key connected directly and an S parameter of a structure where a device under test (DUT) is added between the front-level key and the back-level key. The test module performs S parameter calculation in the frequency domain and converts the S parameter into an ABCD parameter matrix, and then obtains an ABCD parameter of a de-embedded DUT using a matrix root-opening operation and an inverse matrix operation.

Abstract: An arrayed switch circuit includes a substrate, signal conductive pads and signal expansion pins. The signal conductive pads are disposed on the substrate at intervals, and the signal conductive pads are arranged to form a signal conductive pad array. Each of the signal conductive pads has a row position and a column position in the signal conductive pad array. A row signal switch is provided between any two adjacent signal conductive pads corresponding to the same row position, and a column signal switch is provided between any two adjacent signal conductive pads corresponding to the same column position. The signal expansion pins are connected to the signal conductive pads located on at least one side of the signal conductive pad array through signal expansion switches respectively.

Abstract: An arrayed switch circuitry includes contact units each of which includes a pad, a first row channel provided with a first switching element, a first column channel connected to the first row channel and provided with a second switching element, a connecting channel connecting the pad to the first row channel or the first column channel, a second row channel connected with the pad through a third switching element and a second column channel connected with the pad through a fourth switching element. The first row channels with the same row position are connected to each other, and the second row channels with the same row position are connected to each other. The first column channels with the same column position are connected to each other, and the second column channels with the same column position are connected to each other.

Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.

Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.

Abstract: A position-encoding device includes a sensing device, a filtering device, a calibrating device and a compensating device. The sensing device senses the motion of a moving device to generate first and second signals. The filtering device filters the first and second signals to generate first and second filtering signal. The calibrating device captures the first and second filtering signals to obtain time and phase information of the first and second filtering signals, performs gain and offset calibration on the first and second filtering signals, and performs a phase calibration on the first and second filtering signals through first, second feedback signals and the time and phase information of the first and second filtering signals to generate first and second calibrating signals. The compensating device compensates for the first and second calibrating signals according to a lookup table, so as to generate first and second position encoding signals.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

Abstract: A neural circuit is provided. The neural circuit includes a neural array. The neural array includes a plurality of semiconductor components. Each of the semiconductor components stores a weighting value to generate a corresponding output current or a corresponding equivalent resistance. The neural array receives a plurality of input signals to control the semiconductor components in the neural array and respectively generates the output currents or changes the equivalent resistances. Since the semiconductor components are coupled to each other, output of the neural array may generate a summation current or a summation equivalent resistance related to the input signals and a weighting condition, so that a computing result exhibits high performance.

Abstract: A position-encoding device includes a sensing device, a filtering device, a calibrating device and a compensating device. The sensing device senses the motion of a moving device to generate first and second signals. The filtering device filters the first and second signals to generate first and second filtering signal. The calibrating device captures the first and second filtering signals to obtain time and phase information of the first and second filtering signals, performs gain and offset calibration on the first and second filtering signals, and performs a phase calibration on the first and second filtering signals through first, second feedback signals and the time and phase information of the first and second filtering signals to generate first and second calibrating signals. The compensating device compensates for the first and second calibrating signals according to a lookup table, so as to generate first and second position encoding signals.

Abstract: A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.

Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

Abstract: A method of manufacturing a sensor device is provided. In the method, sensing electrodes are formed on a substrate, a sensing material layer is formed on the sensing electrodes. The sensing material layer is etched to form a first nanowire sensing region, a second nanowire sensing region and a third nanowire sensing region respectively between every two sensing electrodes of the sensing electrodes. A dielectric layer is formed to cover the first nanowire sensing region, the second nanowire sensing region and the third nanowire sensing region, and the first nanowire sensing region and the third nanowire sensing region are exposed.

Abstract: A sensor device and a method of manufacturing the same are provided. The sensor device includes a substrate, a plurality of sensing electrodes, a humidity nanowire sensor, a temperature nanowire sensor, and a gas nanowire sensor. The sensing electrodes are formed on the substrate, and the humidity, the temperature and the gas nanowire sensors are also on the substrate. The humidity nanowire sensor includes an exposed first nanowire sensing region, the temperature nanowire sensor includes a second nanowire sensing region, and the gas nanowire sensor includes a third nanowire sensing region.

Abstract: A sensor interface circuit and sensor output adjusting method are provided. The sensor interface circuit includes a processor and a gain control circuit. The processor obtains information of a linear region of a sensor to set a configuration corresponding to the sensor. The gain control circuit is coupled to the processor, performs a return-to-zero operation for a maximum electronic value and a minimum electronic value corresponding to the linear region and performs a full-scale operation for a slope of the linear region according to the maximum input range of an analog-to-digital converter which is a subsequent-stage circuit of the sensor interface circuit.