Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.

Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process.

Abstract: A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.

Abstract: Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.

Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Abstract: Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.

Abstract: A method for making gate-oxide with step-graded thickness (S-G GOX) in a trenched DMOS device is proposed. First, a substrate is provided and a silicon oxide-silicon nitride-silicon oxide (ONO) protective composite layer is formed atop. Second, an upper interim trench (UIT), an upper trench protection wall (UTPW) and a lower interim trench (LIT) are created into the substrate. Third, the substrate material surrounding the LIT is shaped and oxidized into a desired thick-oxide-layer of thickness T1 and depth D1. Fourth, previously formed UTPW is stripped off from the device in progress, then a thin-gate-oxide of thickness T2 where T2<T1 is formed on the vertical surface of the UIT. Fifth, the UIT and LIT are filled with polysilicon then etched back into a polysilicon layer till its top surface defines a desired thin-gate-oxide depth D2.

Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Abstract: A shielded gate transistor device may include one or more shield electrodes formed in a semiconductor substrate at a first level and one or more gate electrodes formed in the semiconductor substrate at a second level that is different from the first level. One or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield electrodes. At least a portion of the gate electrodes is oriented non-parallel to the one or more shield electrodes. The shield electrodes are electrically insulated from the semiconductor substrate and the one or more gate electrodes are electrically insulated from the substrate and shield electrodes.

Abstract: An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.

Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

Abstract: A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode.

Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Abstract: Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.

Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.

Abstract: A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.