Abstract: A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

Abstract: This invention discloses a circuit for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device driven by a gate driver. The circuit includes a current sense circuit for measuring an unclamped inductive testing (UIS) current that increases with an increase of a pulse width inputted from the gate driver to the MOSFET device wherein the current sensing circuit is provided to turn off the gate driver when a predefined UIS current is reached. The test circuit further includes a MOSFET failure detection circuit connected to a drain terminal of the MOSFET device for measuring a drain voltage change for detecting the MOSFET failure during the UIS test. The test circuit further includes a first switch for switching ON/OFF a power supply to the MOSFET device to and a second switch connected between a drain and source terminal of the MOSFET.

Abstract: A Schottky diode includes at least a trenched opened in a semiconductor substrate doped with a dopant of a first conductivity type wherein the trench is filled with a Schottky junction barrier metal. The Schottky diode further includes one or more dopant region of a second conductivity type surrounding sidewalls of the trench distributed along the depth of the trench for shielding a reverse leakage current through the sidewalls of the trench. The Schottky diode further includes a bottom-doped region of the second conductivity type surrounding a bottom surface of the trench and a top-doped region of the second conductivity type surrounding a top portion of the sidewalls of the trench. In a preferred embodiment, the first conductivity type is a N-type conductivity type and the middle-depth dopant region comprising a P-dopant region.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.

Abstract: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region.

Abstract: This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.

Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of Schottky diodes each having a PN junction disposed on an epitaxial layer near a top surface of a semiconductor substrate wherein the PN junction further includes a counter dopant region disposed in the epitaxial layer for reducing a sudden reversal of dopant profile near the PN junction for preventing an early breakdown in the PN junction.

Abstract: A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.

Abstract: This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming part of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.

Abstract: A semiconductor integrated circuit package having a common source current sensing circuit includes a main die having an integrated circuit, the main die including a source bonding pad and a gate bonding pad disposed on an upper surface, a leadframe having a leadframe pad disposed under the main die, and a monitoring die including a source bonding pad and a gate bonding pad disposed on an upper surface, the monitoring die being coupled to the main die in such manner that the main die source bonding pad is coupled to the monitoring die source bonding pad and the main die gate bonding pad is coupled to the monitoring die gate bonding pad and such that the main die and monitoring die upper surfaces are adjacent to one another.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Abstract: A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.

Abstract: A semiconductor package and method of assembling a semiconductor package is disclosed. The semiconductor package includes a first device mounted on a leadframe and a second device mounted on the leadframe. The leadframe has leads extending to the exterior of the package. An anvil may be used to mount a device on the package. The anvil may include two side portions to support the leads of the package, two end portions connected to the two side portions, and a cutout region.

Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.

Abstract: A semiconductor package includes a lead frame having a plurality of leads and a lead frame pad, the lead frame pad including a die coupled thereto, at least one of the plurality of leads having an external portion sloped upwards relative to a bottom surface of the package, metal connectors connecting the die to the plurality of leads, and a resin body encapsulating the die, metal connectors and at least a portion of the lead frame.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.