Patents by Inventor Sik On Kong
Sik On Kong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8520076Abstract: A liquid crystal display is capable of detecting a failure of a gate driver, and a method of testing the same are provided. The liquid crystal display includes a liquid crystal display panel on which liquid crystal cells connected to thin film transistors (TFTs) located at crossings between gate lines and data lines are formed, a data driver that drives the data lines of the liquid crystal display panel, and a gate driver which includes first to nth stages (n is a natural number larger than 1) formed on the liquid crystal display panel that generates normal scan signals for turning on the TFTs in a normal mode, and that generates test scan signals for turning off the TFTs in a test mode.Type: GrantFiled: May 21, 2008Date of Patent: August 27, 2013Assignee: LG Display Co., Ltd.Inventors: Chang Jae Jang, Chung Sik Kong
-
Patent number: 8356318Abstract: A terminal including a wireless communication unit configured to receive broadcast guide information, and a control unit configured to determine whether or not broadcast information included in the received broadcast guide information corresponds to an actual broadcast operation for a corresponding broadcast program, and to update the broadcast guide information when the broadcast information included in the received broadcast guide information does not correspond to the actual broadcast operation for the corresponding broadcast program.Type: GrantFiled: November 20, 2008Date of Patent: January 15, 2013Assignee: LG Electronics Inc.Inventors: Bo Soo Kim, Kwang Sik Kong, Sung Joon Ryu, So Yeon Kim
-
Patent number: 8217575Abstract: A plasma display panel (PDP) including: first and second opposing substrates; a discharge layer disposed between the substrates, having discharge cells; address electrodes disposed on the first substrate, extending in a first direction, across the discharge cells; and display electrodes disposed on the second substrate, extending across the discharge cells in a second direction. The discharge layer includes: a discharge enhancement layer disposed on the first substrate, having first spaces; and a barrier rib layer disposed on the discharge enhancement layer, having second spaces that are connected to the first spaces, so as to form the discharge cells. The discharge enhancement layer further includes a perimeter member disposed in a dummy area provided at the edges of an effective area of the PDP.Type: GrantFiled: October 11, 2010Date of Patent: July 10, 2012Assignee: Samsung SDI Co., Ltd.Inventors: Soon-Dong Jeong, Jae-Huy Park, Kyoung-Sik Jeon, Sun-Sik Kong, Bon-Joo Koo, Jung-Min Kim, Young-Soo Seo, Hyoung-Bin Park, Yu-Il Jang, Sung-Mun Ryu, Chong-In Chung, Sang-Hyuck Ahn, Jung-Sup Kwak
-
Publication number: 20110084604Abstract: A plasma display panel (PDP) including: first and second opposing substrates; a discharge layer disposed between the substrates, having discharge cells; address electrodes disposed on the first substrate, extending in a first direction, across the discharge cells; and display electrodes disposed on the second substrate, extending across the discharge cells in a second direction. The discharge layer includes: a discharge enhancement layer disposed on the first substrate, having first spaces; and a barrier rib layer disposed on the discharge enhancement layer, having second spaces that are connected to the first spaces, so as to form the discharge cells. The discharge enhancement layer further includes a perimeter member disposed in a dummy area provided at the edges of an effective area of the PDP.Type: ApplicationFiled: October 11, 2010Publication date: April 14, 2011Inventors: Soon-Dong Jeong, Jae-Huy Park, Kyoung-Sik Jeon, Sun-Sik Kong, Bon-Joo Koo, Jung-Min Kim, Young-Soo Seo, Hyoung-Bin Park, Yu-Il Jang, Sung-Mun Ryu, Chong-In Chung, Sang-Hyuck Ahn, Jung-Sup Kwak
-
Publication number: 20090204996Abstract: A terminal including a wireless communication unit configured to receive broadcast guide information, and a control unit configured to determine whether or not broadcast information included in the received broadcast guide information corresponds to an actual broadcast operation for a corresponding broadcast program, and to update the broadcast guide information when the broadcast information included in the received broadcast guide information does not correspond to the actual broadcast operation for the corresponding broadcast program.Type: ApplicationFiled: November 20, 2008Publication date: August 13, 2009Inventors: Bo Soo Kim, Kwang Sik Kong, Sung Joon Ryu, So Yeon Kim
-
Publication number: 20080309605Abstract: A liquid crystal display is capable of detecting a failure of a gate driver, and a method of testing the same are provided. The liquid crystal display includes a liquid crystal display panel on which liquid crystal cells connected to thin film transistors (TFTs) located at crossings between gate lines and data lines are formed, a data driver that drives the data lines of the liquid crystal display panel, and a gate driver which includes first to nth stages (n is a natural number larger than 1) formed on the liquid crystal display panel that generates normal scan signals for turning on the TFTs in a normal mode, and that generates test scan signals for turning off the TFTs in a test mode.Type: ApplicationFiled: May 21, 2008Publication date: December 18, 2008Inventors: Chang Jae Jang, Chung Sik Kong
-
Patent number: 6822268Abstract: A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.Type: GrantFiled: May 13, 2003Date of Patent: November 23, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yung-Tao Lin, Sik On Kong
-
Patent number: 6815239Abstract: Five new methods for the formation of an improved liquid-crystal-on-silicon display are described, in which the device structure is enhanced by the photolithographic building of alignment posts among the mirror pixels of the micro-display. These five methods accommodate the fabrication of an optical interference multilayer, which improves the image quality of the reflected light. These five methods are: Silicon Dioxide Posts by Wet Etching. Amorphous Silicon Posts by Plasma Etching. Silicon Nitride Posts by Plug Filling. Insulation Material Posts by Lift-off. Polyimide Posts by Photosensitive Etching.Type: GrantFiled: March 5, 1999Date of Patent: November 9, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sik On Kong, Rajan Rajgopal, George Wong
-
Patent number: 6759857Abstract: A new method and apparatus for detecting and measuring the level of metal present on the surface of a substrate is achieved. Energy, in the form of rf or light or microwave energy, is directed at the surface of a wafer, the reflected energy or the energy that passes through the semiconductor substrate is captured and analyzed for energy level and/or frequency content. Based on this analysis conclusions can be drawn regarding presence and type of metal on the surface of the wafer. Furthermore, by inclusion of metal within the resonating circuit of an rf generator changes the frequency of the vibration and therefore detects the presence of metal.Type: GrantFiled: September 27, 2002Date of Patent: July 6, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sik On Kong, Tsui Ping Chu
-
Publication number: 20030203526Abstract: A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.Type: ApplicationFiled: May 13, 2003Publication date: October 30, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Yung-Tao Lin, Sik On Kong
-
Patent number: 6633170Abstract: A new method and apparatus for detecting and measuring the level of metal present on the surface of a substrate is achieved. Energy, in the form of rf or light or microwave energy, is directed at the surface of a wafer, the reflected energy or the energy that passes through the semiconductor substrate is captured and analyzed for energy level and/or frequency content. Based on this analysis conclusions can be drawn regarding presence and type of metal on the surface of the wafer. Furthermore, by inclusion of metal within the resonating circuit of an rf generator changes the frequency of the vibration and therefore detects the presence of metal.Type: GrantFiled: September 30, 2002Date of Patent: October 14, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sik On Kong, Tsui Ping Chu
-
Patent number: 6569699Abstract: A method of fabricating an LCD-on-silicon pixel device including the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.Type: GrantFiled: February 1, 2000Date of Patent: May 27, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yung-Tao Lin, Sik On Kong
-
Patent number: 6569762Abstract: In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accommodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack.Type: GrantFiled: June 11, 2002Date of Patent: May 27, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventor: Sik On Kong
-
Patent number: 6538333Abstract: In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accomodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack.Type: GrantFiled: June 11, 2002Date of Patent: March 25, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventor: Sik On Kong
-
Publication number: 20030042915Abstract: A new method and apparatus for detecting and measuring the level of metal present on the surface of a substrate is achieved. Energy, in the form of rf or light or microwave energy, is directed at the surface of a wafer, the reflected energy or the energy that passes through the semiconductor substrate is captured and analyzed for energy level and/or frequency content. Based on this analysis conclusions can be drawn regarding presence and type of metal on the surface of the wafer. Furthermore, by inclusion of metal within the resonating circuit of an rf generator changes the frequency of the vibration and therefore detects the presence of metal.Type: ApplicationFiled: September 27, 2002Publication date: March 6, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Sik On Kong, Tsui Ping Chu
-
Publication number: 20030038642Abstract: A new method and apparatus for detecting and measuring the level of metal present on the surface of a substrate is achieved. Energy, in the form of rf or light or microwave energy, is directed at the surface of a wafer, the reflected energy or the energy that passes through the semiconductor substrate is captured and analyzed for energy level and/or frequency content. Based on this analysis conclusions can be drawn regarding presence and type of metal on the surface of the wafer. Furthermore, by inclusion of metal within the resonating circuit of an rf generator changes the frequency of the vibration and therefore detects the presence of metal.Type: ApplicationFiled: September 30, 2002Publication date: February 27, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Sik On Kong, Tsui Ping Chu
-
Patent number: 6476604Abstract: A new method and apparatus for detecting and measuring the level of metal present on the surface of a substrate is achieved. Energy, in the form of rf or light or microwave energy, is directed at the surface of a wafer, the reflected energy or the energy that passes through the semiconductor substrate is captured and analyzed for energy level and/or frequency content. Based on this analysis conclusions can be drawn regarding presence and type of metal on the surface of the wafer. Furthermore, by inclusion of metal within the resonating circuit of an rf generator changes the frequency of the vibration and therefore detects the presence of metal.Type: GrantFiled: April 12, 1999Date of Patent: November 5, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sik On Kong, Tsui Ping Chu
-
Publication number: 20020160598Abstract: In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accommodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack.Type: ApplicationFiled: June 11, 2002Publication date: October 31, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventor: Sik On Kong
-
Publication number: 20020155692Abstract: In the present invention a high performance package is desribed where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accomodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack.Type: ApplicationFiled: June 11, 2002Publication date: October 24, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventor: Sik On Kong
-
Patent number: 6444576Abstract: In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accommodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack.Type: GrantFiled: June 16, 2000Date of Patent: September 3, 2002Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventor: Sik On Kong