Abstract: A method of fabricating an LCD-on-silicon device, comprising the following steps. A semiconductor structure having a control transistor formed therein is provided. The control transistor having a source and a drain. An interlevel dielectric (ILD) layer over the semiconductor structure is provided. Source/drain (S/D) plugs contacting the source and drain through contact openings in said ILD layer are provided. M1 lines are formed over the ILD layer and connected to at least the S/D plugs. An M1 intermetal dielectric (IMD) layer is deposited and patterned over the M1 lines to form M1 contact openings exposing at least some of the M1 metal lines. M1 metal plugs are formed within the M1 contact openings and M2 metal islands connected to, and integral with, at least the M1 metal plugs. The M2 metal islands having exposed side walls. Sidewall spacers are formed on the exposed M2 metal islands side walls.

Abstract: An EEPROM MOSFET memory device with a floating gate and control gate stack above source and drain regions formed in a substrate self-aligned with the stack. There is a means for writing data to the floating gate electrode by applying an upwardly stepwise increasing control gate voltage V.sub.CG1 waveform applied to the control gate of the EEPROM device. The waveform is a voltage ramp providing a substantially constant tunneling current into the floating gate electrode which is approximately constant with respect to time so programming speed and the number of write/erase cycles is increased. The means for threshold voltage testing compares the voltage of the drain electrode to a reference potential.

Abstract: A process is described for generating, through ion implantation, any desired concentration profile. This is accomplished by providing a set of mono-energetic doping concentration profiles which, when superimposed, generate the desired concentration profile (in a manner analogous to generating a square wave by superimposing multiple sine waves). The ion current, accelerating voltage, and dose needed to generate each member of the set is then computed and fed as input to software that controls the operation of the implanter. The various profiles from the set are then implemented while the ion beam remains stationary, thereby generating the desired profile at that spot. The beam is then moved to the next intended location and the process is repeated. In an alternative embodiment, each profile in the set is implemented over the entire surface scanned by the beam and then the process is successively repeated for the remaining members of the set.

Abstract: The present invention relates to a chip-size package (CSP) semiconductor, which comprises a chip having a bonding pad formed at the center portion thereof; a substrate for seating and mounting the chip thereon, which has a predetermined shaped slot formed at the center portion thereof and is formed with a signal circuit pattern on, at least, one surface thereof; an adhesive means inserted between the chip and the substrate for attaching and fixing the chip to the upper surface of the substrate so that the bonding pad of the chip may arrange above the slot; a support and protection means for protecting and supporting the chip and the substrate; and the bonding pad of the chip and the signal circuit pattern of the substrate are electrically interconnected by wire, thus forming internal circuit, thus mass-producing at low price, easily radiated its heat occurring during the operation, thus extending its durability, and improving a reliance of the package and shortening the length of the process.