Abstract: A driving circuit is provided, a driving unit of the driving circuit includes: a control unit utilized to control an output of a stage transmission signal; a stage transmission signal latch unit utilized to receive the stage transmission signal for generating a latch signal; a first and second scanning signal generation units; a first inverted output unit utilized to invert the first scanning signal; a second inverted output unit utilized to invert the second scanning signal. A configuration of a GOA circuit can be simplified.

Abstract: A driving circuit and a shift register circuit are disclosed. The driving circuit includes a plurality of cascaded multi-stages shift register circuits. Each of the shift register circuit includes a transmission door latch circuit and a signal transmission circuit. The transmission door latch circuit includes a transmission door, first clock signals triggering the transmission door such that transmission signals of two stages ahead are transmitted to the signal transmission circuit via the transmission door to generate transmission signals for the current stage. Second clock signals control the transmission signals of the current stage to pass through the signal transmission circuit to generate gate driving signals for the current stage. In this way, the driving circuit is feasible for CMOS manufacturing process, and owns the advantages such as low power consumption and high noise tolerance.

Abstract: A driving circuit is provided, a driving unit of the driving circuit includes: a control unit utilized to control an output of a stage transmission signal; a stage transmission signal latch unit utilized to receive the stage transmission signal for generating a latch signal; a first and second scanning signal generation units; a first inverted output unit utilized to invert the first scanning signal; a second inverted output unit utilized to invert the second scanning signal. A configuration of a GOA circuit can be simplified.

Abstract: The present invention discloses a TFT substrate and a display device. The TFT substrate comprises a scan line, a data line and a common electrode covering the scan line and the data line, wherein the data line and the scan line are disposed in a stagger, in order to divide the crosswise formed region into a plurality of pixel units; the common electrode comprises a plurality of common electrode units and a plurality of bridging portions overlapping with the scan lines and the data lines, wherein the common electrode unit and the pixel unit are correspondingly disposed, each bridging portion is connected with at least two adjacent common electrodes in order to make all of the common electrodes be electrically connected. Through the above ways, the present invention can reduce the RC constant and power consumption, thereby improving the product quality.

Abstract: The present invention discloses a gate drive circuit and a shift register. The gate drive circuit comprises a plurality of shift register circuits which are cascade connected, and each of the shift register circuits comprises a clock control transmission circuit and a NOR gate latch circuit, wherein the clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a gate drive pulse of a former stage to the NOR gate latch circuit, and the NOR gate latch circuit performs latch, and the NOR gate latch circuit is further triggered by a second clock pulse following the first clock pulse to output the gate drive pulse. With the aforesaid arrangement, the gate drive circuit of the present invention is applicable to CMOS process, and the power consumption is low and the noise margin is wide.

Abstract: An array substrate includes a first glass substrate, a first metallic layer for forming a scan line and a gate of a TFT, a first insulating layer on the first metallic layer, a semiconductor layer on the first insulating layer, a second metallic layer disposed on the semiconductor layer for forming a source and a drain of the TFT and a data line, a color resist layer on the second metallic layer and the first insulting layer for forming a color filter, a pixel electrode on the color resist layer and connected to the drain of the TFT through a via hole on the color resist layer, a passivation layer on the electrode layer, and a black matrix layer on the passivation layer. The black matrix is disposed correspondingly to the color filter and the pixel electrode. Using such array substrate can reduce manufacturing processes and cost.

Abstract: The present invention discloses a gate drive circuit and a shift register. The gate drive circuit comprises a plurality of shift register circuits which are cascade connected, and each of the shift register circuits comprises a clock control transmission circuit and a NOR gate latch circuit, wherein the clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a gate drive pulse of a former stage to the NOR gate latch circuit, and the NOR gate latch circuit performs latch, and the NOR gate latch circuit is further triggered by a second clock pulse following the first clock pulse to output the gate drive pulse. With the aforesaid arrangement, the gate drive circuit of the present invention is applicable to CMOS process, and the power consumption is low and the noise margin is wide.

Abstract: The invention provides a NAND gate latched driving circuit and a NAND gate latched shift register. The NAND gate latched driving circuit includes multiple cascade connected shift register circuits, each of the shift register circuits including a clock control transmission circuit and a NAND gate latch circuit. The clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a driving pulse of a former stage to the NAND gate latch circuit, the driving pulse then is latched by the NAND gate latch circuit. The NAND gate latch circuit further is triggered by a subsequent second clock pulse of a first clock signal to output the latched driving pulse. By the above solution, the NAND gate latched driving circuit of the invention is suitable for CMOS process and can achieve low power consumption and wide noise tolerance.

Abstract: A liquid crystal display device and a gate driving circuit are provided. The gate driving circuit includes shift register circuits cascade-connected in series. Each shift register circuit includes: first and second pull-up circuits, first and second pull-down circuits and a pull-down control circuit. The first and second pull-up circuits are electrically connected in series between a preceding-stage gate driving signal and a gate driving signal output terminal. The first and second pull-down circuits and the pull-down control circuit are electrically connected with the first and second pull-up circuits in parallel. The pull-down control circuit is electrically coupled to the preceding-stage gate driving signal, the first and second pull-down circuits and first and second voltage levels and for controlling the first and second pull-down circuits according to the preceding-stage gate driving signal. Accordingly, the invention is suitable for CMOS process and can increase circuit stability.

Abstract: A doping method and a doping apparatus of an array substrate are provided. The doping method includes: providing a substrate defined with to-be-heavily-doped region, to-be-lightly-doped region and to-be-doped channel region; forming a photoresist layer by a lithography process, the photoresist layer including first through third photoresist portions respectively corresponding to the to-be-heavily-doped region, the to-be-lightly-doped region and the to-be-doped channel region, the first photoresist portion being thinner than the second photoresist portion, the second photoresist portion being thinner than the third photoresist portion; and performing one time of doping on the to-be-heavily-doped region, the to-be-lightly-doped region and the to-be-doped region through the photoresist layer and thereby forming a heavily-doped region, a lightly-doped region and a channel region respectively.

Abstract: A liquid crystal panel is disclosed. The liquid crystal panel includes a first substrate, a second substrate, and a liquid crystal layer between the first substrate and the second substrate. The first substrate includes a plurality of pixels respectively corresponding to one pixel electrode. The pixel electrode includes a plurality of primary electrodes and a plurality of branch electrodes extending from the primary electrodes. The second substrate includes a base substrate and a common electrode layer formed on the base substrate. The common electrode layer includes a plurality of recessed portions facing toward the base substrate, and each of the recessed portions faces toward one corresponding primary electrode of the pixel electrode. In this way, the liquid crystal efficiency of pixels is enhanced and an applicable range of ultra-high-resolution, small-sized panels of VA mode may be extended.

Abstract: A liquid crystal display (LCD) panel and a manufacturing method thereof and an array substrate are provided. A pixel unit of the LCD panel includes a liquid crystal layer interposed between first and second substrates, and a first electrode layer, a second electrode layer and an insulating layer arranged on a side of the first substrate. The first electrode layer is neighboring with the first substrate, and the insulating layer is between the first and second electrode layers. The second electrode layer is formed with an electrode pattern, and the insulating layer is formed with grooves corresponding to regions without the electrode pattern of the second electrode layer. Accordingly, a driving voltage of the LCD panel can be reduced while ensuring the display quality, the power consumption is reduced and thereby the work hour of display terminal using the LCD panel is increased.

Abstract: The invention provides a display device and a gate driving circuit thereof. The gate driving circuit includes shift register circuits cascade connected in series. Each shift register circuit includes: first and second pull-up circuits, a first capacitor, a first pull-down circuit including a third transistor, a second pull-down circuit including a fourth transistor, and a pull-down control circuit electrically coupled to preceding-stage gate and succeeding-stage gate driving signals, gates of the third and fourth transistors, and first and second voltage levels. The pull-down control circuit is for controlling the third and fourth transistors according to the preceding-stage and the succeeding-stage gate driving signals. Accordingly, the invention is suitable for CMOS process and can increase circuit stability.

Abstract: The invention provides a GOA driving circuit applied for a flat panel display device and a flat panel display device. The GOA driving circuit includes a front-stage circuit, a middle-stage circuit and a rear-stage circuit. GOA driving subunits in the front-stage circuit, the middle-stage circuit and the rear-stage circuit receive a first clock signal and a second clock signal to sequentially generate corresponding gate driving signals. The first clock signal and the second clock signal are set with an interruption period to generate an interruption between the sequentially generated gate driving signals. The flat panel display device performs a touch detection operation in the interruption period. By the above solution, the invention can achieve the interruption of GOA driving circuit scan and thereby increase touch scan frequency.

Abstract: An FFS array substrate and a liquid crystal display device having the same are disclosed. The FFS array substrate includes a substrate, first metal layer, a first insulated layer, a second metal layer, a second insulated layer, a transparent electrode layer, a third insulated layer and a common-electrode layer. The common-electrode layer includes a common-electrode line having a low resistivity and a transparent common electrode. The FFS array substrate ensures the stability of electrical potential on common electrode and enhances the display effect of the liquid crystal display device.

Abstract: An FFS mode array substrate and an LCD panel having the FFS array substrate are provided. The FFS array substrate includes a base substrate, a first metal layer, a first insulation layer, a second metal layer, a second insulation layer, a common electrode layer, a third insulation layer, and a transparent electrode layer; wherein the common electrode layer includes a common electrode line and a transparent common electrode, and a resistivity of the common electrode line is lower than a resistivity of the transparent common electrodes. This can assure stability of the electric potentials of the common electrodes, and thereby the display performance of an LCD display device having the FFS array substrate is improved.

Abstract: The present invention provides a pixel structure and a manufacturing method thereof. The pixel structure includes: a transparent substrate (60), a gate line formed on the transparent substrate (60), a thin-film transistor formed on the transparent substrate (60), a data line (68) formed on the transparent substrate (60), a pixel electrode (62) formed on the transparent substrate (60) and the thin-film transistor, a passivation layer (64) formed on the pixel electrode (62), the transparent substrate (60), and the data line (68), and a common electrode (66) formed on the passivation layer (64). The passivation layer (64) includes: a first portion (72) located on the data line (68), a second portion (74) located on the pixel electrode (62), and a third portion (76) located on the transparent substrate (60) and arranged on two opposite sides of the data line (68). The first portion (72) of the passivation layer (64) has a thickness greater than a thickness of the second portion (74).

Abstract: The LCD panel includes a first substrate having a first electrode, a second substrate having a second electrode and an opaque area, and a liquid crystal layer located between the first substrate and the second substrate. The opaque area is located within a vertical projection area projected by the first electrode. A protrusion structure is disposed on the first electrode or the second electrode. The protrusion structure is located within a vertical projection area projected by the opaque area. An alignment film is coated on a surface of the protrusion structure such that each liquid crystal molecule in the liquid crystal layer located between the first electrode and the second electrode has a pretilt angle. Through the above method, the present invention can increase the light transmittance, and reduce the number of the mask and the cost.

Abstract: The present invention provides a pixel structure, which includes: a substrate (12), a lower common electrode (14), a gate line (26), a first passivation layer (16), a data line (28), a pixel electrode (18), a second passivation layer (22), and an upper common electrode (24). The first passivation layer (16) includes a first via hole. The second passivation layer (22) includes a second via hole. The lower common electrode (14) is connected through the first and second via holes to the upper common electrode (24). The lower common electrode (14) and the pixel electrode (18) partially overlap each other to form a first capacitor. The upper common electrode (24) and the pixel electrode (18) partially overlap each other to form a second capacitor. The first and second capacitors constitute a storage capacitor of the pixel structure.

Abstract: The present disclosure provides a method for producing spacers in a liquid crystal panel, comprising: (a) exposing a material layer adjacent to a side of a thin film transistor substrate of said liquid crystal panel by a mask with a pre-set pattern, in order to form a groove in said material layer, wherein the exposure energy of said exposure ranges from 10 to 100 mJ/cm2; (b) forming a main spacer and a side spacer in an opposite substrate, wherein the height of the side spacer is higher than that of the main spacer; and (c) assembling a TFT array substrate and the opposite substrate together, such that the main spacer of the opposite substrate abuts against the TFT array substrate, and the side spacer extends into said groove. The present disclosure also provides a liquid crystal panel obtained by said method.