Abstract: An array substrate and a reflective display substrate are disclosed. The array substrate includes a base, and a plurality of data lines and a plurality of sub-pixels that are disposed on the base. The sub-pixel includes a reflective pixel electrode and a TFT. An orthographic projection of the pixel electrode in each sub-pixel on the base is overlapped with orthographic projections of a first electrode, a first data line and a second data line.

Abstract: An array substrate and a reflective display substrate are disclosed. The array substrate includes a base, and a plurality of data lines and a plurality of sub-pixels that are disposed on the base. The sub-pixel includes a reflective pixel electrode and a TFT. An orthographic projection of the pixel electrode in each sub-pixel on the base is overlapped with orthographic projections of a first electrode, a first data line and a second data line.

Abstract: An array substrate and a reflective display substrate are disclosed. The array substrate includes a base, and a plurality of data lines and a plurality of sub-pixels that are disposed on the base. The sub-pixel includes a reflective pixel electrode and a TFT. An orthographic projection of the pixel electrode in each sub-pixel on the base is overlapped with orthographic projections of a first electrode, a first data line and a second data line.

Abstract: The present application provides a shift register and a method of driving the same, and a gate driving circuit. In the shift register, an input sub-circuit is configured to output an input signal to a pull-up node under control of a first clock signal of a first clock signal terminal, an output sub-circuit is configured to output a second clock signal of a second clock signal terminal to the output terminal under control of a voltage level of the pull-up node, a reset sub-circuit is configured to reset voltage levels of the pull-up node and the output terminal under control of a voltage level of a pull-down node, and a reset control sub-circuit is configured to control the voltage level of the pull-down node such that the voltage levels of the pull-up node and the output terminal are reset to a level signal.

Abstract: Provided are a shift register unit of a gate driving circuit (GOA), a gate driving circuit and a driving method. The shift register unit includes an input sub-circuit, configured to output an input signal to a first node; a pull-up control sub-circuit, configured to charge a pull-up node through a first power supply terminal under the control of a potential of the first node; an output sub-circuit, configured to output a clock signal of a clock signal terminal to an output terminal under the control of a potential of the pull-up node; a first touch control sub-circuit configured to pull down levels of the pull-up node and the output terminal to a second potential through the second power supply terminal under the control of a touch control keeping signal of the touch control keeping signal terminal.

Abstract: The present application provides a shift register and a method of driving the same, and a gate driving circuit. In the shift register, an input sub-circuit is configured to output an input signal to a pull-up node under control of a first clock signal of a first clock signal terminal, an output sub-circuit is configured to output a second clock signal of a second clock signal terminal to the output terminal under control of a voltage level of the pull-up node, a reset sub-circuit is configured to reset voltage levels of the pull-up node and the output terminal under control of a voltage level of a pull-down node, and a reset control sub-circuit is configured to control the voltage level of the pull-down node such that the voltage levels of the pull-up node and the output terminal are reset to a level signal.

Abstract: Embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an inputting sub-circuit, an outputting sub-circuit, a resetting sub-circuit, a pulling-down sub-circuit, a pulling-down controlling sub-circuit, and a voltage regulating sub-circuit. The voltage regulating sub-circuit is coupled to a pulling-down node, a pulling-down controlling node, a second clock signal terminal, a third clock signal terminal, a first voltage signal terminal and a second voltage signal terminal, and is configured to regulate a voltage at the pulling-down controlling node based on a first voltage signal from the first voltage signal terminal and a second voltage signal from the second voltage signal terminal, under a control of the second clock signal from the second clock signal terminal, a third clock signal from the third clock signal terminal, and the voltage at the pulling-down node.

Abstract: A shift register includes a first input sub-circuit, a first output sub-circuit, and a second output sub-circuit. The first input sub-circuit is connected to a first input terminal, a pull-up node, and a first control terminal, and the first input sub-circuit is configured to output a voltage of the first control terminal to the pull-up node under control of a voltage of the first input terminal. The first output sub-circuit is connected to the pull-up node, a clock signal terminal, and an output terminal, and the first output sub-circuit is configured to output a first level of the clock signal terminal to the output terminal under control of a voltage of the pull-up node. The second output sub-circuit is connected to the output terminal, a second output control terminal, and a first voltage terminal, and the second output sub-circuit is configured to output a voltage of the first voltage terminal to the output terminal under control of a voltage of the second output control terminal.

Abstract: Provided are a shift register unit of a gate driving circuit (GOA), a gate driving circuit and a driving method. The shift register unit includes an input sub-circuit, configured to output an input signal to a first node; a pull-up control sub-circuit, configured to charge a pull-up node through a first power supply terminal under the control of a potential of the first node; an output sub-circuit, configured to output a clock signal of a clock signal terminal to an output terminal under the control of a potential of the pull-up node; a first touch control sub-circuit configured to pull down levels of the pull-up node and the output terminal to a second potential through the second power supply terminal under the control of a touch control keeping signal of the touch control keeping signal terminal.

Abstract: A shift register, a gate drive circuit, a display panel, and a driving method. The shift register includes: an input circuit, which is connected to a pull-up node and an input signal terminal respectively; an output circuit, which is connected to the pull-up node, a clock signal terminal, a direct current signal terminal and an input terminal respectively, wherein the clock signal terminal provides a clock signal, the direct current signal terminal provides a direct current signal, and the output circuit outputs a scanning signal from the output terminal; and an output pull-down circuit, which is connected to the output circuit. The output circuit is configured to output a scanning signal from the output terminal as one from among the direct current signal and the clock signal when a first output condition is satisfied.

Abstract: Embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an inputting sub-circuit, an outputting sub-circuit, a resetting sub-circuit, a pulling-down sub-circuit, a pulling-down controlling sub-circuit, and a voltage regulating sub-circuit. The voltage regulating sub-circuit is coupled to a pulling-down node, a pulling-down controlling node, a second clock signal terminal, a third clock signal terminal, a first voltage signal terminal and a second voltage signal terminal, and is configured to regulate a voltage at the pulling-down controlling node based on a first voltage signal from the first voltage signal terminal and a second voltage signal from the second voltage signal terminal, under a control of the second clock signal from the second clock signal terminal, a third clock signal from the third clock signal terminal, and the voltage at the pulling-down node.

Abstract: According to one aspect of this disclosure, a scanning trigger unit includes a clock signal terminal, a first signal input terminal, a fixed level signal terminal, a first input sub-circuit, an output sub-circuit, a first holding sub-circuit, and a signal output terminal. The first input sub-circuit is connected to the first signal input terminal and a control node, and is configured to provide a first valid signal to the control node; the output sub-circuit is connected to the fixed level signal terminal, the clock signal terminal, and the control node, and is configured to provide a second valid signal to the signal output terminal; and the first holding sub-circuit is connected to the fixed level signal terminal and the signal output terminal, and is configured to hold the second valid signal at the signal output terminal for a predetermined time.

Abstract: A shift register includes a first input sub-circuit, a first output sub-circuit, and a second output sub-circuit. The first input sub-circuit is connected to a first input terminal, a pull-up node, and a first control terminal, and the first input sub-circuit is configured to output a voltage of the first control terminal to the pull-up node under control of a voltage of the first input terminal. The first output sub-circuit is connected to the pull-up node, a clock signal terminal, and an output terminal, and the first output sub-circuit is configured to output a first level of the clock signal terminal to the output terminal under control of a voltage of the pull-up node. The second output sub-circuit is connected to the output terminal, a second output control terminal, and a first voltage terminal, and the second output sub-circuit is configured to output a voltage of the first voltage terminal to the output terminal under control of a voltage of the second output control terminal.

Abstract: A touch display substrate, a driving method of a touch display substrate, and a touch display device. The touch display substrate includes: a base substrate; a plurality of electrode patterns on the base substrate; signal lines in one-to-one correspondence with the electrode patterns; a compensation circuit on the base substrate, wherein the compensation circuit is configured to provide a common voltage signal to the electrode patterns in response to a touch control signal.

Abstract: A shift register circuit, a driving method, a gate driving circuit and a display device are provided. The shift register circuit includes an input circuit; a reset circuit; a first pull-up node control circuit; a second pull-up node control circuit for controlling the pull-up node to couple to the second level output terminal when a potential of the pull-down node is a first level; a first pull-down node control circuit for controlling the potential of the pull-down node being the first level in the reset phase; a second pull-down node control circuit for controlling the pull-down node to couple to the second level output terminal when the potential of the pull-up node is the first level; a gate drive signal output circuit; and a carry signal output circuit for controlling the carry signal output terminal to output a carry signal under control of the pull-up node and the pull-down node.

Abstract: A shift register circuit, a driving method, a gate driving circuit, and a display device are provided. The shift register circuit includes a clock signal adjustment circuit and a self-control conduction circuit; the clock signal adjustment circuit includes a first clock signal input terminal, a second clock signal input terminal, and a clock signal adjustment output terminal; the clock signal adjusting circuit is configured to, in the case that the first clock signal and the second clock signal are both at a second level, output a first level via a clock signal adjustment output terminal; the self-control conduction circuit is configured to, in the case that the pull-up node is at the first level, control the clock signal adjustment output terminal connect with a pull-up node, or in the case that the pull-up node is at a second level, disconnect the clock signal adjustment output terminal from the pull-up node.

Abstract: A shift register circuit, a driving method, a gate driving circuit and a display device are provided. The shift register circuit includes an input circuit; a reset circuit; a first pull-up node control circuit; a second pull-up node control circuit for controlling the pull-up node to couple to the second level output terminal when a potential of the pull-down node is a first level; a first pull-down node control circuit for controlling the potential of the pull-down node being the first level in the reset phase; a second pull-down node control circuit for controlling the pull-down node to couple to the second level output terminal when the potential of the pull-up node is the first level; a gate drive signal output circuit; and a carry signal output circuit for controlling the carry signal output terminal to output a carry signal under control of the pull-up node and the pull-down node.

Abstract: A shift register and driving method thereof, a gate driving circuit and a display apparatus are provided. The shift register includes an input unit, a reset unit, a first control unit, a second control unit, a first output unit, a second output unit, a first signal output end and a second signal output end. Potential of the first signal output end is controlled by use of the input unit, the reset unit, the first control unit and the first output unit, and potential of the second signal output end is controlled by use of the input unit, the reset unit, the second control unit and the second output unit. The first control unit and the first output unit, the second control unit and the second output unit are utilized for controlling and sharing the input unit and the reset unit so that function of two shift register units are realized.

Abstract: A shift register, a gate drive circuit, a display panel, and a driving method. The shift register includes: an input circuit, which is connected to a pull-up node and an input signal terminal respectively; an output circuit, which is connected to the pull-up node, a clock signal terminal, a direct current signal terminal and an input terminal respectively, wherein the clock signal terminal provides a clock signal, the direct current signal terminal provides a direct current signal, and the output circuit outputs a scanning signal from the output terminal; and an output pull-down circuit, which is connected to the output circuit. The output circuit is configured to output a scanning signal from the output terminal as one from among the direct current signal and the clock signal when a first output condition is satisfied.

Abstract: A shift register circuit, a driving method, a gate driving circuit, and a display device are provided. The shift register circuit includes a clock signal adjustment circuit and a self-control conduction circuit; the clock signal adjustment circuit includes a first clock signal input terminal, a second clock signal input terminal, and a clock signal adjustment output terminal; the clock signal adjusting circuit is configured to, in the case that the first clock signal and the second clock signal are both at a second level, output a first level via a clock signal adjustment output terminal; the self-control conduction circuit is configured to, in the case that the pull-up node is at the first level, control the clock signal adjustment output terminal connect with a pull-up node, or in the case that the pull-up node is at a second level, disconnect the clock signal adjustment output terminal from the pull-up node.