Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs having insulative material atop treads of the stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Conductive vias extend through the insulative material. Individual of the conductive vias are directly above and directly against the conducting material of the respective individual tread. A lining is over sidewalls of the individual conductive vias. The lining has a bottom. The individual conductive vias are directly under the bottom of the lining directly above the conducting material of the respective individual tread.

Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures.

Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

Abstract: A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.

Abstract: A method of forming a semiconductor device comprising forming a silicon carbide material on a patterned material. The silicon carbide material is subjected to a plasma to expose horizontal portions of the silicon carbide material to the plasma. The horizontal portions of the silicon carbide material are selectively removed, and the patterned material is removed to form a pattern of the silicon carbide material.

Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: A vertical transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The top source/drain region and the channel region have a top interface and the bottom source/drain region and the channel region have a bottom interface. The channel region is crystalline and has an average crystal grain size of its crystal grains that is less than 20 nanometers. The channel region at the top interface or at the bottom interface has greater horizontal texture than volume of the crystal grains in the channel region that is vertically between the crystal grains that are at the top and bottom interfaces. Other embodiments and aspects are disclosed.

Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.

Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.

Abstract: Apparatus (e.g., semiconductor devices) include stack structures with at least one conductive region and at least one nonconductive material. A multidielectric spacer is adjacent the at least one conductive region and comprises first and second dielectric materials. The first dielectric material, adjacent the at least one conductive region, includes silicon and nitrogen. The second dielectric material, adjacent the first dielectric material, comprises silicon-carbon bonds and defines a substantially straight, vertical, outer sidewall. In methods to form such apparatus, the first dielectric material may be formed with selectivity on the at least one conductive region, and the second dielectric material may be formulated and formed to exhibit etch resistance.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.

Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.