Patents by Inventor Silvia Borsari

Silvia Borsari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111184
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 15, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Cole Smith, Ramey M. Abdelrahaman, Silvia Borsari, Chris M. Carlson, David Daycock, Matthew J. King, Jin Lu
  • Patent number: 10971500
    Abstract: A method used in fabrication of integrated circuitry comprises forming metal material outwardly of a substrate. At least a majority (i.e., up to and including 100%) of the metal material contains ruthenium in at least one of elemental-form, metal compound-form, or alloy-form. A masking material is formed outwardly of the ruthenium-containing metal material. The masking material comprises at least one of nine specifically enumerated materials or category of materials. The masking material is used as a mask while etching through an exposed portion of the ruthenium-containing metal material to form a feature of integrated circuitry that comprises the ruthenium-containing metal material.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ying Rui, Tong Liu, Yi Fang Lee, Davide Colombo, Silvia Borsari, Austin Johnson
  • Publication number: 20210098463
    Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
  • Patent number: 10937690
    Abstract: Methods, apparatuses, and systems related to selectively depositing a liner material on a sidewall of an opening are described. An example method includes forming a liner material on a dielectric material of sidewalls of an opening and a bottom surface of an opening and removing the first liner material of the sidewalls of the opening and the bottom surface of the opening using a non-selective etch chemistry. The example method further includes forming a second liner material on the dielectric material of the sidewalls of the opening to avoid contact with the bottom surface of the opening.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anish Khandekar, Lars P. Heineck, Silvia Borsari, Zhiqiang Xie
  • Patent number: 10886282
    Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
  • Publication number: 20200388622
    Abstract: A method used in fabrication of integrated circuitry comprises forming metal material outwardly of a substrate. At least a majority (i.e., up to and including 100%) of the metal material contains ruthenium in at least one of elemental-form, metal compound-form, or alloy-form. A masking material is formed outwardly of the ruthenium-containing metal material. The masking material comprises at least one of nine specifically enumerated materials or category of materials. The masking material is used as a mask while etching through an exposed portion of the ruthenium-containing metal material to form a feature of integrated circuitry that comprises the ruthenium-containing metal material.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Ying Rui, Tong Liu, Yi Fang Lee, Davide Colombo, Silvia Borsari, Austin Johnson
  • Publication number: 20200373304
    Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Inventors: Silvia Borsari, Stian E. Wood, Haoyu Li, Yiping Wang
  • Patent number: 10818667
    Abstract: Some embodiments include an integrated assembly having semiconductor material structures which each have a transistor channel region, and which are over metal-containing structures. Carbon-doped oxide is adjacent regions of each of the semiconductor material structures and sidewalls of the metal-containing structures. Some embodiments include an integrated assembly having pillars of semiconductor material. Each of the pillars has four sidewalls. Two of the four sidewalls of each pillar are gated sidewalls. The other two of the four sidewalls are non-gated sidewalls. Carbon-doped silicon dioxide is adjacent and directly against the non-gated sidewalls. Some embodiments include a method of forming an integrated assembly. Rails of semiconductor material are formed. A layer of carbon-doped silicon dioxide is formed adjacent top surfaces and sidewall surfaces of each of the rails. Trenches are formed which slice the semiconductor material of the rails into pillars.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Silvia Borsari, Sau Ha Cheung
  • Publication number: 20200312712
    Abstract: Methods, apparatuses, and systems related to selectively depositing a liner material on a sidewall of an opening are described. An example method includes forming a liner material on a dielectric material of sidewalls of an opening and a bottom surface of an opening and removing the first liner material of the sidewalls of the opening and the bottom surface of the opening using a non-selective etch chemistry. The example method further includes forming a second liner material on the dielectric material of the sidewalls of the opening to avoid contact with the bottom surface of the opening.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Anish Khandekar, Lars P. Heineck, Silvia Borsari, Zhiqiang Xie
  • Publication number: 20200286898
    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
  • Publication number: 20200235005
    Abstract: Apparatus (e.g., semiconductor devices) include stack structures with at least one conductive region and at least one nonconductive material. A multidielectric spacer is adjacent the at least one conductive region and comprises first and second dielectric materials. The first dielectric material, adjacent the at least one conductive region, includes silicon and nitrogen. The second dielectric material, adjacent the first dielectric material, comprises silicon-carbon bonds and defines a substantially straight, vertical, outer sidewall. In methods to form such apparatus, the first dielectric material may be formed with selectivity on the at least one conductive region, and the second dielectric material may be formulated and formed to exhibit etch resistance.
    Type: Application
    Filed: January 17, 2019
    Publication date: July 23, 2020
    Inventors: John A. Smythe, Silvia Borsari, Francois H. Fabreguette, Sutharsan Ketharanathan
  • Publication number: 20200235103
    Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
  • Patent number: 10700073
    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
  • Publication number: 20200111796
    Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
  • Patent number: 10615165
    Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Amirhasan Nourbakhsh, John K. Zahurak, Sanh D. Tang, Silvia Borsari, Hong Li
  • Patent number: 10607936
    Abstract: A method of forming an elevationally-extending conductor laterally between a pair of structures comprises forming a pair of structures individually comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line and the conductive via respectively have opposing sides in a vertical cross-section. Elevationally-extending-insulative material is formed along the opposing sides of the conductive via and the conductive line in the vertical cross-section. The forming of the insulative material comprises forming a laterally-inner-insulator material comprising silicon, oxygen, and carbon laterally-outward of the opposing sides of the conductive via and the conductive line in the vertical cross-section. A laterally-intervening-insulator material comprising silicon and oxygen is formed laterally-outward of opposing sides of the laterally-inner-insulator material in the vertical cross-section.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Silvia Borsari
  • Publication number: 20190378843
    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.
    Type: Application
    Filed: May 22, 2019
    Publication date: December 12, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
  • Publication number: 20190348419
    Abstract: Some embodiments include an integrated assembly having semiconductor material structures which each have a transistor channel region, and which are over metal-containing structures. Carbon-doped oxide is adjacent regions of each of the semiconductor material structures and sidewalls of the metal-containing structures. Some embodiments include an integrated assembly having pillars of semiconductor material. Each of the pillars has four sidewalls. Two of the four sidewalls of each pillar are gated sidewalls. The other two of the four sidewalls are non-gated sidewalls. Carbon-doped silicon dioxide is adjacent and directly against the non-gated sidewalls. Some embodiments include a method of forming an integrated assembly. Rails of semiconductor material are formed. A layer of carbon-doped silicon dioxide is formed adjacent top surfaces and sidewall surfaces of each of the rails. Trenches are formed which slice the semiconductor material of the rails into pillars.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Silvia Borsari, Sau Ha Cheung
  • Patent number: 10381352
    Abstract: Some embodiments include an integrated assembly having semiconductor material structures which each have a transistor channel region, and which are over metal-containing structures. Carbon-doped oxide is adjacent regions of each of the semiconductor material structures and sidewalls of the metal-containing structures. Some embodiments include an integrated assembly having pillars of semiconductor material. Each of the pillars has four sidewalls. Two of the four sidewalls of each pillar are gated sidewalls. The other two of the four sidewalls are non-gated sidewalls. Carbon-doped silicon dioxide is adjacent and directly against the non-gated sidewalls. Some embodiments include a method of forming an integrated assembly. Rails of semiconductor material are formed. A layer of carbon-doped silicon dioxide is formed adjacent top surfaces and sidewall surfaces of each of the rails. Trenches are formed which slice the semiconductor material of the rails into pillars.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Silvia Borsari, Sau Ha Cheung
  • Patent number: 10347643
    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky