Patents by Inventor Sim Lee
Sim Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210175157Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.Type: ApplicationFiled: December 1, 2020Publication date: June 10, 2021Inventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
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Publication number: 20210166988Abstract: A semiconductor package includes a die pad having a die attach surface, a first laterally separated and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and comprising a first terminal on an upper surface of the semiconductor die, an interconnect clip that is electrically connected to the first terminal and to the first lead, and a heat spreader mounted on top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends past an outer edge side of the die pad. The heat spreader covers an area of the first planar section that is larger than an area of the semiconductor die. The heat spreader laterally extends past a first outer edge side of the die pad that faces the first lead.Type: ApplicationFiled: December 2, 2019Publication date: June 3, 2021Inventors: Jo Ean Joanna Chye, Teck Sim Lee, Ke Yan Tean, Wei-Shan Wang
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Publication number: 20210074614Abstract: A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.Type: ApplicationFiled: September 4, 2020Publication date: March 11, 2021Inventors: Ralf Otremba, Teck Sim Lee, Lee Shuang Wang, Mohd Hasrul Zulkifli
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Publication number: 20210020539Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.Type: ApplicationFiled: July 15, 2020Publication date: January 21, 2021Applicant: Infineon Technologies AGInventors: Ralf Otremba, Teck Sim Lee, Klaus Schiess, Xaver Schloegel, Lee Shuang Wang, Mohd Hasrul Zulkifli
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Patent number: 10727151Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.Type: GrantFiled: May 25, 2017Date of Patent: July 28, 2020Assignee: Infineon Technologies AGInventors: Liu Chen, Teck Sim Lee, Jia Yi Wong, Wei Han Koo, Thomas Stoeck, Gilles Delarozee
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Patent number: 10699978Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.Type: GrantFiled: September 7, 2018Date of Patent: June 30, 2020Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Amirul Afiq Hud, Teck Sim Lee, Xaver Schloegel, Bernd Schmoelzer
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Patent number: 10639427Abstract: The invention relates to an injection device with a luer fitting. The injection device has a compressible syringe body defining a reservoir. A male luer fitting has a channel therethrough for conducting contents of the reservoir, and a luer tip at an end of said male luer fitting opposing said base end. A first connecting structure is arranged on said male luer fitting between said base end and said luer tip. A shield cap is arranged on the male luer fitting. The shield cap has a second connecting structure interacting with said first connecting structure to prevent inadvertent movement of said shield cap relative to said male luer fitting when said shield cap is arranged at said first position. A first seal is provided for sealing said channel at said luer tip and a second seal is provided for sealing the outer surface and the luer tip.Type: GrantFiled: November 11, 2016Date of Patent: May 5, 2020Assignee: Becton, Dickinson and CompanyInventors: Neville Yu Leng Chia, Roderick Hausser, Xua Huyen Nguyen Huu, Hoong Sim Lee, Hong Tat Teddy Lim
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Patent number: 10450225Abstract: The present invention relates to a glass having a surface with improved water-repellency or hydrophobicity and low reflectance, and a fabrication method thereof. A technology is employed, in which a thin film containing silicon or silicon oxide is formed on the glass surface, the nano-structures are formed by selective etching treatment using a reactive gas such as CF4 or the like to provide superhydrophobicity and low reflectance properties, and a material with low surface energy is coated onto the nano-structures. The fabrication method of the low-reflective and superhydrophobic or super water-repellent glass may execute deposition and etching processes for the glass having the superhydrophobicity and the low reflectance, and provide excellent superhydrophobicity and low reflectance to the surface of the glass which was difficult to be treated. Also, the method is sustainable due to non-use of a toxic etching solution during these processes.Type: GrantFiled: December 2, 2014Date of Patent: October 22, 2019Assignee: Korea Institute of Science and TechnologyInventors: Myoung Woon Moon, Heon Ju Lee, Jeong Sim Lee, Tae Jun Ko, Kyu Hwan Oh, Do Hyun Kim, Eu Sun Yu
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Patent number: 10373897Abstract: A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.Type: GrantFiled: December 13, 2016Date of Patent: August 6, 2019Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Ralf Otremba, Felix Grawert, Amirul Afiq Hud, Uwe Kirchner, Teck Sim Lee, Guenther Lohmann, Hwee Yin Low, Edward Fuergut, Bernd Schmoelzer, Fabian Schnoy, Franz Stueckler
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Patent number: 10290567Abstract: A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, a second chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal, and a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge.Type: GrantFiled: September 1, 2017Date of Patent: May 14, 2019Assignee: Infineon Technologies AGInventors: Rainald Sander, Liu Chen, Teck Sim Lee
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Publication number: 20190080973Abstract: A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.Type: ApplicationFiled: September 7, 2018Publication date: March 14, 2019Inventors: Ralf Otremba, Amirul Afiq Hud, Teck Sim Lee, Xaver Schloegel, Bernd Schmoelzer
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Publication number: 20190074243Abstract: A package which comprises an electrically conductive chip carrier, a first chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, a second chip comprising a first connection terminal, a second connection terminal located on the chip carrier and a control terminal, wherein the first chip and the second chip are connected to form a half bridge having inlet terminals and an outlet terminal, and a clip having three connection sections connecting the second connection terminal of the first chip with the first connection terminal of the second chip and with the outlet terminal of the half bridge.Type: ApplicationFiled: September 1, 2017Publication date: March 7, 2019Inventors: Rainald SANDER, Liu CHEN, Teck Sim LEE
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Patent number: 10204845Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.Type: GrantFiled: August 28, 2017Date of Patent: February 12, 2019Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
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Patent number: 10147703Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.Type: GrantFiled: March 24, 2017Date of Patent: December 4, 2018Assignee: Infineon Technologies AGInventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
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Publication number: 20180342438Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.Type: ApplicationFiled: May 25, 2017Publication date: November 29, 2018Inventors: Liu Chen, Teck Sim Lee, Jia Yi Wong, Wei Han Koo, Thomas Stoek, Gilles Delarozee
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Publication number: 20180277513Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.Type: ApplicationFiled: March 24, 2017Publication date: September 27, 2018Inventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
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Patent number: 10083899Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.Type: GrantFiled: January 23, 2017Date of Patent: September 25, 2018Assignee: Infineon Technologies AGInventors: Mohd Kahar Bajuri, Edmund Sales Cabatbat, Gaylord Evangelista Cruz, Amirul Afiq Hud, Teck Sim Lee, Norbert Joson Santos, Chiew Li Tai, Chin Wei Yang
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Patent number: 10037934Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.Type: GrantFiled: February 4, 2016Date of Patent: July 31, 2018Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Chooi Mei Chong, Raynold Talavera Corocotchia, Teck Sim Lee, Sanjay Kumar Murugan, Klaus Schiess, Chee Voon Tan, Wee Boon Tay
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Publication number: 20180211907Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.Type: ApplicationFiled: January 23, 2017Publication date: July 26, 2018Inventors: Mohd Kahar Bajuri, Edmund Sales Cabatbat, Gaylord Evangelista Cruz, Amirul Afiq Hud, Teck Sim Lee, Norbert Joson Santos, Chiew Li Tai, Chin Wei Yang
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Publication number: 20180158758Abstract: A method of manufacturing a hybrid leadframe is provided comprising providing a thin leadframe layer comprising a diepad and a structured region and attaching a metal layer on the diepad, wherein the metal layer has a thickness which is larger than a thickness of the thin leadframe layer.Type: ApplicationFiled: February 6, 2018Publication date: June 7, 2018Inventors: Ralf OTREMBA, Chooi Mei Chong, Josef Hoeglauer, Teck Sim Lee, Klaus Schiess, Xaver Schloegel