Abstract: A stack of interleaved wipes where the first wipe (10) will have its first crease (15) drawn to the region of or partially through an opening (1) in a container (2) of the wipes, so that it can be grasped and drawn through the opening. The second wipe (20) and those below are in their interleaved arrangement. The crease (25) together with adjoining parts of the portions (21, 24), is enfolded in a fold (170) of the wipe (10) formed by its portions (11, 16) and the crease (17). The wipe (10) is the wipe next to the wipe (20) on its side opposite from its portions (24, 26). The crease (27) at the opposite edge from crease (25) of the main portion (21) forms with the main portion (21) and the second folded portion (26) a fold (270) which enfolds the fold (350) of the wipe (30).

Abstract: A stack of interleaved wipes where the first wipe (10) will have its first crease (15) drawn to the region of or partially through an opening (1) in a container (2) of the wipes, so that it can be grasped and drawn through the opening. The second wipe (20) and those below are in their interleaved arrangement. The crease (25) together with adjoining parts of the portions (21, 24), is enfolded in a fold (170) of the wipe (10) formed by its portions (11, 16) and the crease (17). The wipe (10) is the wipe next to the wipe (20) on its side opposite from its portions (24, 26). The crease (27) at the opposite edge from crease (25) of the main portion (21) forms with the main portion (21) and the second folded portion (26) a fold (270) which enfolds the fold (350) of the wipe (30).

Abstract: A register data store 20 is provided within a data processing system 2. The register data store 20 may be accessed via registers for which a data processing instruction specifies a register size Q, D and a data element size S16, S8 for the multiple SIMD data elements to be manipulated by that data processing instruction. A given data processing element may be accessed via different registers depending upon the mapping between the register specifier, the register size and the data element size to a particular location within the register data store 20.

Abstract: A parallel processing technique is described for performing parallel processing operations upon N-dimensional arrays of data elements for which a corresponding N-dimensional Scoreboard of status data is held. Hazard checking for data dependencies upon data elements within the N-dimensional array of data elements is performed by looking up the corresponding status value within the Scoreboard. The status data for a given data element within the Scoreboard is located at a position which can be derived from the position of the data elements within its N-dimensional array. Thus, a two-dimensional array of video macroblocks can have a corresponding two-dimensional Scoreboard of status data indicating whether individual macroblocks have, for example, either already been deblocked or have not already been deblocked.

Abstract: A data processing apparatus operate to process floating point operands is disclosed. The data processing apparatus comprises: an instruction decoder operable to decode an instruction for processing floating point operands; and a data processor operable to perform data processing operations controlled by the instruction decoder wherein: in response to the decoded instruction indicating operation according to a flush-to-zero semantic, the data processor is operable to process the floating point operands in accordance with the decoded instruction such that floating point operands having a denormal value are treated as zero operands; and in response to the decoded instruction indicating operation according to a denormal semantic, the data processor is operable to process the floating point operands in accordance with the decoded instruction such that floating point operands having a denormal value are treated as denormal operands.

Abstract: A data processing apparatus operable to map an input data value 10 to a resultant data value 50 is disclosed, said data processing apparatus comprising: a ternary content addressable memory 20 operable to store a plurality of first data values; a data store operable 30 to store a plurality of second data values corresponding to said plurality of first data values; said ternary content addressable memory 20 comprising a data input operable to receive said input data value, said ternary content addressable memory being operable to match said input data value to a first data value and to control said data store to output a second data value corresponding to said matched first data value; said data processing apparatus further comprising exclusive combination logic operable to exclusively combine at least some bits of said output second data value with at least some bits of said input data value to produce at least some bits of said resultant data value.

Abstract: A data processing system (2) is provided including a local memory (4) and a main memory (6). The local memory (4) is accessed by a data engine (8) using local-memory physical addresses. The main memory (6) is accessed by a microprocessor (10) using main-memory addresses. A translation store (16) serves to store physical address TAGs indicating the mapping between data stored within the local memory (4) and corresponding data stored within the main memory (6). A coherency management mechanism (18) serves to use MESI coherency control data to manage the coherency between data values stored both in the local memory (4) and the main memory (6).

Abstract: A computer implemented tool is provided for assisting in the mapping of a computer program to an asymmetric multiprocessing apparatus 2 incorporating an asymmetric memory hierarchy formed of a plurality of memories 12, 14. An at least partial architectural description 22, 40 is provided as an input variable to the tool and used to infer missing annotations within a source computer program 24, such as which functions are to be executed by which execution mechanisms 4, 6, 8 and which variables are to be stored within which memories 12, 14. The tool also adds mapping support commands, such as cache flush commands, cache invalidate commands, DMA move commands and the like as necessary to support the mapping of the computer program to the asymmetric multiprocessing apparatus 2.

Abstract: A method for management of a resource by a community of participants comprising: (a) defining individual tasks necessary for managing the resource; (b) allocating a quantum of redeemable reward points to each defined task; (c) defining participants within the community to execute tasks for reward points; (d) selecting rewards which may be redeemed by surrendering reward points earned by participants and allocation of values to each reward expressed in reward points; (e) providing an information system which enables participants to view and claim available rewards; and (f) providing an information system which keeps track of tasks, points and rewards associated with participants.

Abstract: A data processing apparatus and method of handling conditional instructions in such a data processing apparatus are provided. The data processing apparatus has a pipelined processing unit for executing instructions including at least one conditional instruction from a set of conditional instructions, and a register file having a plurality of registers operable to store data values for access by the pipelined processing unit when executing the instructions. A register specified by an instruction may be either a source register holding a source data value for that instruction or a destination register into which is stored a result data value generated by execution of that instruction. The register file has a predetermined number of read ports via which data values can be read from registers of the register file.

Abstract: Leakage current from a circuit for handling data is reduced using leakage control circuit operable in a leakage reduction mode. The data handling circuit comprises data handling logic operable to receive an input data value and to output and output data value. The data handling circuit also comprises a latch operable to latch the output data value in response to a clock signal having a clock period. Both the leakage control circuitry and the latch are controlled dependent upon the same clock signal and the leakage control circuitry is controlled such that it is in a leakage reduction mode for a time less than the clock period. This approach enables leakage reduction to be provided in circuits which are still operational and is particularly suited to data handling circuits that employ frequency scaling.

Abstract: Data processing apparatus and methods are provided. One data processing apparatus comprises: a plurality of pipelined stages, each of the plurality pipelined stages being operable in each processing cycle to receive a group of data elements from an earlier pipelined stage; permute logic operable to buffer ‘n’ of the groups of data elements over a corresponding ‘n’ processing cycles thereby creating a bubble within pipelined stages, and forwarding logic operable, once the ‘n’ of the groups of data elements have been buffered by the permute logic, to forward permuted groups of data elements comprising the data elements reordered by the permute logic to fill the bubble within the pipelined stages.

Abstract: The present invention provides a data processing apparatus and method for generating an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data processing apparatus comprises processing logic for executing instructions to perform data processing operations on data, and a lookup table referenced by the processing logic during generation of the initial estimate of the result value. The processing logic is responsive to an estimate instruction to reference the lookup table to generate, dependent on a modified input value that is within a predetermined range of values, a table output value. For a particular modified input value, the same table output value is generated irrespective of whether the input value is a fixed point value or a floating point value. The initial estimate of the result value is then derivable from the table output value.

Abstract: A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result register D3. Out-of-range index values result in the corresponding locations within the result register being left unchanged U. In this way, an offset can be applied to index values held and then those index values reused with the table registers D0, D1 being reloaded with a different portion of a table so as to give the effect of a larger table than can be directly supported by the number of table registers available.

Abstract: A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination value with the remaining bits within that destination value being unaltered.

Abstract: A data processing apparatus, method and computer program product.

Abstract: A register data store 20 is provided within a data processing system 2. The register data store 20 may be accessed via registers for which a data processing instruction specifies a register size Q, D and a data element size S16, S8 for the multiple SIMD data elements to be manipulated by that data processing instruction. A given data processing element may be accessed via different registers depending upon the mapping between the register specifier, the register size and the data element size to a particular location within the register data store 20.

Abstract: The present invention provides a data processing apparatus and method for performing data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to decode a data processing instruction in order to determine a corresponding data processing operation to be performed by the processing logic. The data processing instruction has an m-bit immediate value encoded therein. Further, constant generation logic is provided to perform a logical operation on the m-bit immediate value in order to generate an n-bit floating point constant for use as at least one input floating point data element for the processing logic when performing the corresponding data processing operation. The values “n” and “m” are integers, and n is greater than m. This approach provides a particularly efficient technique for generating floating point constants.

Abstract: A data processing apparatus and method are provided for performing in parallel a data processing operation on data elements. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and processing logic operable to perform data processing operations on data elements. A decoder is operable to decode a data processing instruction, the data processing instruction identifying a lane size and a data element size, the lane size being a multiple of the data element size. Further, the decoder is operable to control the processing logic to define based on the lane size a number of lanes of parallel processing in at least one of the registers, and the processing logic is operable to perform in parallel a data processing operation on the data elements within each lane of parallel processing. This provides significantly improved flexibility in the performance of SIMD operations.

Abstract: A data processing system 2 is provided including a scalar register store 4 and a SIMD register store 20. Dedicated register transfer instructions are provided which serve to move a data value between a selected data element position/lane within a SIMD register of the SIMD register data store 20 and a scalar register within the scalar register store 4. This type of register transfer instruction allows particular data elements to be picked out of and inserted into a SIMD register in a manner which advantageously improves overall efficiency. A further type of register transfer instruction is provided which copies a data value taken from a scalar register into all positions of a specified SIMD register.