Patents by Inventor Simon Ford

Simon Ford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050125637
    Abstract: A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor. (18) operable to perform data processing operations within parallel processing lanes on at least one source operand in response to a data processing instruction decoded by said instruction decoder (16); and said data processor being operable in response to said decoded instruction with generated constant and associated data value to expand at least a data portion (1210) of said associated data value, said expansion being performed in response to said instruction with generated constant and depending on a selected function, to generate a constant (1240), said generated constant (1240) forming one of said at least one source operands.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Wilco Dijkstra, Simon Ford, David Seal
  • Publication number: 20050125631
    Abstract: Within a SIMD processor 2 data processing instructions are provided which specify parallel lanes of processing to be performed upon respective data elements. The data elements are permitted to vary in size whilst the number of processing lanes remain constant. Thus, the destination register size for a multiplication may be double the source register size.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Dominic Symes, Simon Ford, Daniel Kershaw, David Seal
  • Publication number: 20050125624
    Abstract: The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to perform a data processing operation on one or more data elements accessed in at least one of the registers. Further, access logic is provided which is operable in response to an access instruction to perform an access operation in order to move a number of data elements between specified registers and a portion of a memory, the portion having a start address specified by the access instruction. Further, the access instruction has an alignment specifier associated therewith which is settable either to a first value or one of a plurality of second values.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Andrew Rose, Simon Ford, Dominic Symes, David Seal
  • Publication number: 20050125639
    Abstract: A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result register D3. Out-of-range index values result in the corresponding locations within the result register being left unchanged U. In this way, an offset can be applied to index values held and then those index values reused with the table registers D0, D1 being reloaded with a different portion of a table so as to give the effect of a larger table than can be directly supported by the number of table registers available.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Dominic Symes, Simon Ford, Andrew Rose
  • Publication number: 20050125640
    Abstract: A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Simon Ford, Dominic Symes, Andrew Rose, David Lutz, Christopher Hinds
  • Publication number: 20050125476
    Abstract: A data processing apparatus, method and a computer program product.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Dominic Symes, Simon Ford
  • Publication number: 20050125635
    Abstract: A data processing system 2 is provided including a scalar register store 4 and a SIMD register store 20. Dedicated register transfer instructions are provided which serve to move a data value between a selected data element position/lane within a SIMD register of the SIMD register data store 20 and a scalar register within the scalar register store 4. This type of register transfer instruction allows particular data elements to be picked out of and inserted into a SIMD register in a manner which advantageously improves overall efficiency. A further type of register transfer instruction is provided which copies a data value taken from a scalar register into all positions of a specified SIMD register.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Dominic Symes, Simon Ford
  • Publication number: 20050125647
    Abstract: A memory system can store data in either a big endian mode or a little endian mode. Memory accessing logic 810 utilises byte invariant addressing to retrieve multiple data elements from that memory to be stored within a SIMD register 812. Data element reordering logic 808 is responsive to an endianess mode specifying signal and a data element size specifying signal to reorder retrieved bytes such that the data elements when stored within the SIMD registers 812 are invariant irrespective of the endianess mode being used by the memory.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Dominic Symes, Simon Ford
  • Publication number: 20050125641
    Abstract: A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Simon Ford, Dominic Symes, Andrew Rose, David Lutz, Christopher Hinds
  • Publication number: 20050125638
    Abstract: A data processing apparatus and method.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Simon Ford, Dominic Symes, Daniel Kershaw
  • Publication number: 20050125636
    Abstract: A data processing apparatus is disclosed. The apparatus comprises a register data store comprising a plurality of registers. The apparatus further comprises a data processor operable to perform in parallel a data processing operation on data elements; and decode logic responsive to a single vector-by-scalar instruction to control the data processor so as to specify one of the plurality of registers as a first source register operable to store a plurality of source data elements, to specify another of the plurality of registers as a second source register operable to store a plurality of selectable data elements, to select one of said selectable data elements as a scalar operand and to perform a vector-by-scalar operation in parallel on the source data elements, each vector-by-scalar operation causing a resultant data element to be generated from a source data element and the scalar operand.
    Type: Application
    Filed: July 13, 2004
    Publication date: June 9, 2005
    Applicant: ARM LIMITED
    Inventors: Simon Ford, Dominic Symes, Daniel Kershaw, Andrew Rose