Abstract: A NOR gate including a pull-down circuit coupled to a pull-up circuit. The NOR gate is configured to drive an output signal to a low logic state at a substantially uniform slew rate regardless of the number of input signals that are in high logic state. The pull-down circuit may include a first plurality of transistor circuits each coupled to a corresponding one of the plurality of input signals, and a second plurality of transistor circuits each comprising a plurality of transistors coupled in parallel with each other and coupled to a corresponding one of the plurality of input signals or a complement of a corresponding one of the plurality of input signals. The first and second plurality of transistor circuits may each include an n-channel MOS (NMOS) transistor. The NOR gate may be incorporated into a decoder of a synchronous or asynchronous input path circuit to generally reduce the set-up and hold time window of the input path circuit.

Abstract: A circuit including an address bus providing random addresses for a random access memory array, and a register configured to receive, store or transfer (i) a first random address from the address bus in response to a first periodic signal transition and (ii) a second random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle, and are preferably complementary to each other.

Abstract: A NAND gate including a pull-down circuit coupled to a pull-up circuit. The NAND gate is configured to drive an output signal to a high logic state at a substantially uniform slew rate regardless of the number of input signals that are in a low logic state. The pull-up circuit may include a plurality of load circuits each coupled to a corresponding one of the plurality of input signals, and a plurality of transistor circuits each comprising a plurality of transistors coupled in parallel with each other and coupled to a corresponding one of the plurality of input signals or a complement of a corresponding one of the plurality of input signals. The plurality of load circuits and the plurality of transistors may each include a p-channel MOS (PMOS) transistor. The NAND gate may be incorporated into a decoder of a synchronous or asynchronous input path circuit to generally reduce the setup and hold time window of the input path circuit.