Abstract: A high-speed transparent refresh DRAM-based memory cell and architecture are disclosed. Each memory cell consists of 4 transistors configured to incorporate differential data storage (i.e., storing a true logic state and a complementary logic state), with each pair of transistors having a dual port configuration and forming one of a complementary pair of storage nodes for the memory cell. Each memory cell is coupled to 2 wordlines and 4 digit lines. Since the memory cell stores complementary data, and since a logic LOW state is rewritten to a given memory cell faster than a logic HIGH state is rewritten, the logic LOW state is rewritten and the complementary logic state is known to be a logic HIGH state. As a result, both the logic LOW and logic HIGH states are rewritten to the memory cell faster than independently writing a logic HIGH state.

Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

Abstract: An apparatus and method are provided for testing and sorting semiconductor dies based on performance characteristics. A tester is provided that supplies a pulse to an oscillator fabricated in association with a die under test. A counter is provided which counts oscillations of the oscillator to a predetermined value. Once the counter counts to the predetermined value, it provides a signal to the tester. The tester determines the elapsed time between when the oscillator is activated and when the signal is received from the counter and determines the frequency of the oscillator from the elapsed time.

Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

Abstract: A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.

Abstract: An input buffer having a stable trip point over at least process skew and supply voltage variations includes a first inverter stage; a second inverter stage; and an arrangement for compensating for process skew and supply voltage variations. The compensating arrangement is disposed both in the pull-up and pull-down paths, and increases the conductivity of the pull-up path and decreases the conductivity of the pull-down path when the DC trip point of the input buffer falls below nominal. The compensating arrangement also decreases the conductivity of the pull-up path and increases the conductivity of the pull-down path when the DC trip point rises above nominal. The compensating arrangement may include at least one device disposed in each of the pull-up and pull-down paths. The conductivity of these devices may then be controlled by a reference signal that swings about the DC trip point responsive to at least process skew corners and variations in supply voltage.

Abstract: A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.

Abstract: A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.

Abstract: A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.

Abstract: An apparatus and method are provided for testing and sorting semiconductor dies based on performance characteristics. A tester is provided that supplies a pulse to an oscillator fabricated in association with a die under test. A counter is provided which counts oscillations of the oscillator to a predetermined value. Once the counter counts to the predetermined value, it provides a signal to the tester. The tester determines the elapsed time between when the oscillator is activated and when the signal is received from the counter and determines the frequency of the oscillator from the elapsed time.

Abstract: A random access memory with a read port, a write port, a read/write control signal configured to control data transfer operations at the read port and/or the write port on both rising and falling transitions, and a first random access memory array configured to store and/or retrieve data at a first random address in the first random access memory array defined by one or more signals on a write address bus and/or a read address bus. One preferred embodiment further includes a write data register storing or latching data in response to a first transition of the read/write control signal, and the array storing data in response to a second transition of the read/write control signal. Other preferred embodiments further include an n·m-bits-wide input data bus coupling a set of data inputs to the write data register, and/or an n·m-bits-wide output data bus coupling the read data register to a set of data outputs, where n and m are each independently an integer >2.

Abstract: A random access memory with a data input bus, a data output bus, a random access memory array configured to transfer data to random write addresses and from random read addresses in the random access memory array, an address bus providing the random read addresses and the random write addresses, and a first periodic signal configured to control data transfer operations (i) to the random access memory array in response to a first transition of the periodic signal and (ii) from the random access memory array in response to a second transition of the periodic signal, wherein the second transition of the periodic signal is complementary to the first transition of the periodic signal. One preferred embodiment further includes circuitry operable to write data into and read data from the random access memory array. Other preferred embodiments further include a write data register and/or a read data register. In a further embodiment, each of the data input bus and the data output bus is unidirectional.

Abstract: A random access memory with a data input bus, a data output bus, a random access memory array configured to transfer data to random write addresses and from random read addresses in the random access memory array, an address bus providing the random read addresses and the random write addresses, and a first periodic signal configured to control data transfer operations (i) to the random access memory array in response to a first transition of the periodic signal and (ii) from the random access memory array in response to a second transition of the periodic signal, wherein the second transition of the periodic signal is complementary to the first transition of the periodic signal. One preferred embodiment further includes circuitry operable to write data into and read data from the random access memory array. Other preferred embodiments further include a write data register and/or a read data register. In a further embodiment, each of the data input bus and the data output bus is unidirectional.

Abstract: A random access memory with a read port, a write port, a read/write control signal configured to control data transfer operations at the read port and/or the write port on both rising and falling transitions, and a first random access memory array configured to store and/or retrieve data at a first random address in the first random access memory array defined by one or more signals on a write address bus and/or a read address bus. One preferred embodiment further includes a write data register storing or latching data in response to a first transition of the read/write control signal, and the array storing data in response to a second transition of the read/write control signal. Other preferred embodiments further include an n.m-bits-wide input data bus coupling a set of data inputs to the write data register, and/or an n.m-bits-wide output data bus coupling the read data register to a set of data outputs, where n and m are each independently an integer >2.

Abstract: A circuit including an address bus providing random addresses for a random access memory array, and a register configured to receive, store or transfer (i) a first random address from the address bus in response to a first periodic signal transition and (ii) a second random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle, and are preferably complementary to each other.

Abstract: An input buffer having a stable trip point over at least process skew and supply voltage variations includes a first inverter stage; a second inverter stage; and an arrangement for compensating for process skew and supply voltage variations. The compensating arrangement is disposed both in the pull-up and pull-down paths, and increases the conductivity of the pull-up path and decreases the conductivity of the pull-down path when the DC trip point of the input buffer falls below nominal. The compensating arrangement also decreases the conductivity of the pull-up path and increases the conductivity of the pull-down path when the DC trip point rises above nominal. The compensating arrangement may include at least one device disposed in each of the pull-up and pull-down paths. The conductivity of these devices may then be controlled by a reference signal that swings about the DC trip point responsive to at least process skew corners and variations in supply voltage.

Abstract: A random access memory with a read port, a write port, a read/write control signal configured to control data transfer operations at the read port and/or the write port on both rising and falling transitions, and a first random access memory array configured to store and/or retrieve data at a first random address in the first random access memory array defined by one or more signals on a write address bus and/or a read address bus. One preferred embodiment further includes a write data register storing or latching data in response to a first transition of the read/write control signal, and the array storing data in response to a second transition of the read/write control signal. Other preferred embodiments further include an n·m-bits-wide input data bus coupling a set of data inputs to the write data register, and/or an n·m-bits-wide output data bus coupling the read data register to a set of data outputs, where n and m are each independently an integer >2.

Abstract: A random access memory with a data input bus, a data output bus, a random access memory array configured to transfer data to random write addresses and from random read addresses in the random access memory array, an address bus providing the random read addresses and the random write addresses, and a first periodic signal configured to control data transfer operations (i) to the random access memory array in response to a first transition of the periodic signal and (ii) from the random access memory array in response to a second transition of the periodic signal, wherein the second transition of the periodic signal is complementary to the first transition of the periodic signal. One preferred embodiment further includes circuitry operable to write data into and read data from the random access memory array. Other preferred embodiments further include a write data register and/or a read data register. In a further embodiment, each of the data input bus and the data output bus is unidirectional.

Abstract: A circuit comprising a first and a second sense transistor, a bitline and a complementary bitline, one or more first switches and one or more second switches. The first switches may be configured to couple the first sense transistor to the bitline and the second sense transistor to the complementary bitline. The second switches may be configured to couple the first sense transistor to the complementary bitline and the second sense transistor to the bitline. The first and second switches may be configured to provide voltage threshold matching between the first and second transistors.

Abstract: A nonvolatile cell comprising a first device comprising a first transistor type and a second device comprising a second transistor type. The first device may have a gate, a source, a drain and a gate oxide layer over the gate. The second device may have a gate, a source, a drain and a floating gate formed between the gate of said first device and the gate of the second device. The floating gate may be configured to store a charge in response to (i) a first voltage applied to the source and drain of said first device and (ii) a second voltage applied to the source and drain of the second device.