Abstract: To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimated probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated. Preferably, the estimated probability measures are initial probability measures that are transformed to final probability measures under the constraint that the bit pattern(s) (collectively) is/are a member of a candidate set, e.g. a set of codewords.

Abstract: A codeword is decoded by receiving a codeword representation that includes a plurality of soft bits and iteratively updating the soft bits. Whether each soft bit participates in at least some iterations is determined according to a selection criterion, e.g., probabilistically, or according to iteration number, or according to the soft bit's iteration history. For example, each soft bit might participate in some or all iterations with a probability that is a function of both the iteration number and a reliability measure of that soft bit. Preferably, the iterations are LDPC iterations in which variable nodes are addressed sequentially for exchanging messages with corresponding check nodes.

Abstract: To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

Abstract: Data are encoded as a systematic or nonsystematic codeword that is stored in a memory such as a flash memory. A representation of the codeword is read from the memory. A plurality of bits related to the representation of the codeword is decoded iteratively. The plurality of bits could be, for example, part or all of the representation of the codeword itself or part or all of the results of preliminary processing of part or all of the representation of the codeword.

Abstract: A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.

Abstract: To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

Abstract: Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

Abstract: A method and apparatus are disclosed for MAP decoding of signals encoded using error correction codes to make maximum probability decisions about each transmitted bit. A disclosed MAP decoding algorithm extends the work of Hartman and Rudolph and exploits properties of Hamming error correction codes to provide a decoding algorithm having a complexity that is proportional to n log n for Hamming codes. The invention computes a difference, ?, of the probabilities the that transmitted symbol was zero and one based on characteristics of the channel and then determines the product of the ?l values corresponding to non-zero positions of codewords of the dual code using real vector and 2[2]-vector fast Walsh-Hadamard transforms. The invention also processes all positions of all codewords to determine a sum for each position that indicates the reliability that a received bit is a given value for a given position using the real vector fast Walsh-Hadamard transforms.

Abstract: A multi-level flash memory cell is read by comparing the cell's threshold voltage to a plurality of integral reference voltages and to a fractional reference voltage. Multi-level cells of a flash memory are programmed collectively with data and redundancy bits at each significance level, preferably with different numbers of data and redundancy bits at each significance level. The cells are read collectively, from lowest to highest significance level, by correcting the bits at each significance level according to the redundancy bits and adjusting the bits of the higher significance levels accordingly. The adjustment following the correction of the least significant bits is in accordance with comparisons of a cell's threshold voltages to fractional reference voltages.

Abstract: LDPC decoder for decoding a code word (Y) received from a communication channel as the result of transmitting a Low Density Parity Check (LDPC) code word (b) having a number (N) of code word bits which consists of K information bits and N parity check bits, wherein the product of the LDPC code word (b) and a predetermined (M×N) parity check matrix H is zero (H*bT=0) wherein the (M×N) parity check matrix H represents a bipartite graph comprising N variable nodes (V) connected to M check nodes (C) via edges according to matrix elements hij of the parity check matrix H.

Abstract: Method for decoding a noisy codeword (y) received form a communication channel as the result of a Low Density Parity Check (LDPC) codeword (b) having a number (N) of codeword bits which consist of k information bits and M parity check bits, wherein the procuct of the LDPC codeword b and a predetermined (M×N) parity check matrix H is zero (H*bT=0) wherein the parity check matrix H represents a bipartite graph comprising N variable nodes (V) connected to M check nodes (C) via edges according to matrix elements hij of the parity check matrix H, wherein the method comprises the following steps: receiving the noisy LDPC codeword (y) via said communication channel; calculating for each codeword bit (V) of said transmitted LDPC codeword (b) an a-priori estimate (Qv) that the codeword bit has a predetermined value from the received noisy codeword (y) and from predetermined parameters of said communication channel storing the calculated estimates (Qv) for each variable node (V) of said bipartite graph corresponding t

Abstract: Dual Carrier Modulator (DCM) for a Multiband OFDM (Orthogonal Frequency Division Multiplexing) Transceiver of a Ultra Wide Band (UWB) wireless personal access network transmitting OFDM modulated symbols, wherein each OFDM symbol is modulated by a predetermined number (NCBPS) of encoded bits, said Dual Carrier Modulator (1) comprising: (a) a grouping unit (1-1) for grouping NCBPS encoded bits of a serial bit stream into bit groups each having a predetermined number (m) of bits; (b) a mapping unit (1-2) for mapping each bit group received from said grouping unit to complex symbols (y) using an orthogonal transform; and (c) a reordering unit (1-3) for reordering the complex symbols (y) mapped by said mapping unit, wherein each complex symbol (y) is provided to modulate a corresponding data tone of an OFDM symbol.

Abstract: A multi-level flash memory cell is read by comparing the cell's threshold voltage to a plurality of integral reference voltages and to a fractional reference voltage. Multi-level cells of a flash memory are programmed collectively with data and redundancy bits at each significance level, preferably with different numbers of data and redundancy bits at each significance level. The cells are read collectively, from lowest to highest significance level, by correcting the bits at each significance level according to the redundancy bits and adjusting the bits of the higher significance levels accordingly. The adjustment following the correction of the least significant bits is in accordance with comparisons of a cell's threshold voltages to fractional reference voltages.

Abstract: A method and apparatus are disclosed for MAP decoding of signals encoded using error correction codes to make maximum probability decisions about each transmitted bit. A disclosed MAP decoding algorithm extends the work of Hartman and Rudolph and exploits properties of Hamming error correction codes to provide a decoding algorithm having a complexity that is proportional to n log n for Hamming codes. The invention computes a difference, &rgr;, of the probabilities the that transmitted symbol was zero and one based on characteristics of the channel and then determines the product of the &rgr;l values corresponding to non-zero positions of codewords of the dual code using real vector and F2[2]-vector fast Walsh-Hadamard transforms. The invention also processes all positions of all codewords to determine a sum for each position that indicates the reliability that a received bit is a given value for a given position using the real vector fast Walsh-Hadamard transforms.

Abstract: A method for increasing information capacity in nominally m-bit-per-cell Flash technology, using advanced coding techniques and changes in the Flash array interface, without increasing the basic cell size or the bit read failure rate. The increase in information capacity is obtained by using a number n, greater than 1, of memory cells, each cell having a respective adjustable parameter, setting the parameters to collectively represent a binary number of b bits, b being greater than nm, measuring the parameters and decoding the measured parameters collectively to recover the number.